221 lines
4.9 KiB
C
221 lines
4.9 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: smptests.h,v 1.16 1997/07/20 18:10:28 smp Exp smp $
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*/
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#ifndef _MACHINE_SMPTESTS_H_
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#define _MACHINE_SMPTESTS_H_
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/*
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* various 'tests in progress'
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*/
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/*
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* Address of POST hardware port.
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* Defining this enables POSTCODE macros.
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*
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#define POST_ADDR 0x80
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*/
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/*
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* 1st attempt to use ExtInt connected 8259 to attach 8254 timer.
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* failing that, attempt to attach 8254 timer via direct APIC pin.
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* failing that, panic!
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* This overrides both APIC_PIN0_TIMER & TEST_ALTTIMER
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*/
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#define NEW_STRATEGY
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/*
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* Use 'regular Int' method to connect external 8254 timer via IO APIC pin 0.
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* See "Intel I486 Microprocessors and Related Products", page 4-292:
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* 82489DX/8259A DUAL MODE CONNECTION
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*
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*/
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#define APIC_PIN0_TIMER
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/*
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* Use non 'ExtInt' method of external (non-conected) 8254 timer
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* See "Intel I486 Microprocessors and Related Products", page 4-292:
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* 82489DX/8259A DUAL MODE CONNECTION
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*
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*/
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#define TEST_ALTTIMER
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/*
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* Send 8254 timer INTs to all CPUs in LOPRIO mode.
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*
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*/
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#define TIMER_ALL
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/*
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* Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
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*
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*/
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#define CPUSTOP_ON_DDBBREAK
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#define VERBOSE_CPUSTOP_ON_DDBBREAK
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/*
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* Bracket code/comments relevant to the current 'giant lock' model.
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* Everything is now the 'giant lock' model, but we will use this as
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* we start to "push down" the lock.
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*/
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#define GIANT_LOCK
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/*
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* use 'lowest priority' for sending IRQs to CPUs
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*
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* i386/i386/mplock.s, i386/i386/mpapic.c, kern/init_main.c
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*
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*/
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#define TEST_LOPRIO
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/*
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* deal with broken smp_idleloop()
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*/
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#define IGNORE_IDLEPROCS
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/*
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* misc. counters
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*
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#define COUNT_XINVLTLB_HITS
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#define COUNT_SPURIOUS_INTS
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#define COUNT_CSHITS
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*/
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/**
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* hack to "fake-out" kernel into thinking it is running on a 'default config'
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*
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* value == default type
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#define TEST_DEFAULT_CONFIG 6
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*/
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/*
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* simple test code for IPI interaction, save for future...
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*
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#define TEST_TEST1
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#define IPI_TARGET_TEST1 1
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*/
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/*
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* POST hardware macros.
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*/
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#ifdef POST_ADDR
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#define ASMPOSTCODE_INC \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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incl %eax ; \
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andl $0xff, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode value.
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*/
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#define ASMPOSTCODE(X) \
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pushl %eax ; \
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movl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode low nibble.
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*/
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#define ASMPOSTCODE_LO(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0xf0, %eax ; \
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orl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode high nibble.
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*/
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#define ASMPOSTCODE_HI(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0x0f, %eax ; \
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orl $(X<<4), %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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#else
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#define ASMPOSTCODE_INC
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#define ASMPOSTCODE(X)
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#define ASMPOSTCODE_LO(X)
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#define ASMPOSTCODE_HI(X)
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#endif /* POST_ADDR */
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/*
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* these are all temps for debugging...
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*
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#define GUARD_INTS
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*/
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/*
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* This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
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*/
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#ifdef GUARD_INTS
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#define GUARD_CPU 1
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#define MAYBE_PANIC(irq_num) \
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cmpl $GUARD_CPU, _cpuid ; \
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jne 9f ; \
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cmpl $1, _ok_test1 ; \
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jne 9f ; \
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pushl lapic_isr3 ; \
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pushl lapic_isr2 ; \
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pushl lapic_isr1 ; \
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pushl lapic_isr0 ; \
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pushl lapic_irr3 ; \
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pushl lapic_irr2 ; \
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pushl lapic_irr1 ; \
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pushl lapic_irr0 ; \
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pushl $irq_num ; \
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pushl _cpuid ; \
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pushl $panic_msg ; \
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call _printf ; \
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addl $44, %esp ; \
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9:
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#else
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#define MAYBE_PANIC(irq_num)
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#endif /* GUARD_INTS */
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#endif /* _MACHINE_SMPTESTS_H_ */
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