7113afc84c
This patch has the driver for 10Gigabit Ethernet controller in AMD SoC. This driver is written compatible to the Iflib framework. The existing driver is for the old version of hardware. The submitted driver here is for the recent versions of the hardware where the Ethernet controller is PCI-E based. Submitted by: Rajesh Kumar <rajesh1.kumar@amd.com> MFC after: 1 month Relnotes: yes Differential Revision: https://reviews.freebsd.org/D25793
315 lines
8.6 KiB
C
315 lines
8.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2016,2017 SoftIron Inc.
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* Copyright (c) 2020 Advanced Micro Devices, Inc.
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*
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* This software was developed by Andrew Turner under
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* the sponsorship of SoftIron Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _XGBE_OSDEP_H_
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#define _XGBE_OSDEP_H_
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#include <sys/endian.h>
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#include <sys/socket.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/iflib.h>
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MALLOC_DECLARE(M_AXGBE);
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typedef uint16_t __le16;
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typedef uint16_t __be16;
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typedef uint32_t __le32;
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#define BIT(pos) (1ul << pos)
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#define cpu_to_be16(x) be16toh(x)
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#define be16_to_cpu(x) htobe16(x)
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#define lower_32_bits(x) ((x) & 0xffffffffu)
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#define upper_32_bits(x) (((x) >> 32) & 0xffffffffu)
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#define cpu_to_le32(x) le32toh(x)
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#define le32_to_cpu(x) htole32(x)
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#define cpu_to_le16(x) htole16(x)
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#define for_each_set_bit(bit, addr, size) \
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for ((bit) = find_first_bit((addr), (size)); \
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(bit) < (size); \
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(bit) = find_next_bit((addr), (size), (bit) + 1))
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typedef struct mtx spinlock_t;
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static inline void
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spin_lock_init(spinlock_t *spinlock)
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{
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mtx_init(spinlock, "axgbe_spin", NULL, MTX_SPIN);
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}
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#define spin_lock_irqsave(spinlock, flags) \
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do { \
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(flags) = intr_disable(); \
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mtx_lock_spin(spinlock); \
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} while (0)
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#define spin_unlock_irqrestore(spinlock, flags) \
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do { \
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mtx_unlock_spin(spinlock); \
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intr_restore(flags); \
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} while (0)
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#define ADVERTISED_Pause (1 << 0)
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#define ADVERTISED_Asym_Pause (1 << 1)
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#define ADVERTISED_Autoneg (1 << 2)
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#define ADVERTISED_Backplane (1 << 3)
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#define ADVERTISED_10000baseKR_Full (1 << 4)
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#define ADVERTISED_2500baseX_Full (1 << 5)
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#define ADVERTISED_1000baseKX_Full (1 << 6)
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#define ADVERTISED_100baseT_Full (1 << 7)
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#define ADVERTISED_10000baseR_FEC (1 << 8)
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#define ADVERTISED_10000baseT_Full (1 << 9)
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#define ADVERTISED_2500baseT_Full (1 << 10)
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#define ADVERTISED_1000baseT_Full (1 << 11)
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#define ADVERTISED_TP (1 << 12)
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#define ADVERTISED_FIBRE (1 << 13)
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#define ADVERTISED_1000baseX_Full (1 << 14)
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#define ADVERTISED_10000baseSR_Full (1 << 15)
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#define ADVERTISED_10000baseLR_Full (1 << 16)
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#define ADVERTISED_10000baseLRM_Full (1 << 17)
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#define ADVERTISED_10000baseER_Full (1 << 18)
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#define ADVERTISED_10000baseCR_Full (1 << 19)
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#define ADVERTISED_100baseT_Half (1 << 20)
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#define ADVERTISED_1000baseT_Half (1 << 21)
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#define SUPPORTED_Pause (1 << 0)
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#define SUPPORTED_Asym_Pause (1 << 1)
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#define SUPPORTED_Autoneg (1 << 2)
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#define SUPPORTED_Backplane (1 << 3)
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#define SUPPORTED_10000baseKR_Full (1 << 4)
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#define SUPPORTED_2500baseX_Full (1 << 5)
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#define SUPPORTED_1000baseKX_Full (1 << 6)
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#define SUPPORTED_100baseT_Full (1 << 7)
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#define SUPPORTED_10000baseR_FEC (1 << 8)
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#define SUPPORTED_10000baseT_Full (1 << 9)
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#define SUPPORTED_2500baseT_Full (1 << 10)
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#define SUPPORTED_1000baseT_Full (1 << 11)
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#define SUPPORTED_TP (1 << 12)
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#define SUPPORTED_FIBRE (1 << 13)
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#define SUPPORTED_1000baseX_Full (1 << 14)
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#define SUPPORTED_10000baseSR_Full (1 << 15)
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#define SUPPORTED_10000baseLR_Full (1 << 16)
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#define SUPPORTED_10000baseLRM_Full (1 << 17)
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#define SUPPORTED_10000baseER_Full (1 << 18)
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#define SUPPORTED_10000baseCR_Full (1 << 19)
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#define SUPPORTED_100baseT_Half (1 << 20)
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#define SUPPORTED_1000baseT_Half (1 << 21)
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#define LPA_PAUSE_ASYM 0x0800
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#define AUTONEG_DISABLE 0
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#define AUTONEG_ENABLE 1
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#define DUPLEX_UNKNOWN 1
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#define DUPLEX_FULL 2
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#define DUPLEX_HALF 3
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#define SPEED_UNKNOWN 1
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#define SPEED_10000 2
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#define SPEED_2500 3
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#define SPEED_1000 4
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#define SPEED_100 5
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#define SPEED_10 6
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#define BMCR_SPEED100 0x2000
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#define MDIO_MMD_PMAPMD 1
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#define MDIO_MMD_PCS 3
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#define MDIO_MMD_AN 7
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#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
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#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
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#define MDIO_PMA_10GBR_FECABLE 170
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#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
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#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002
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#define MII_ADDR_C45 (1<<30)
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#define MDIO_CTRL1 0x00 /* MII_BMCR */
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#define MDIO_CTRL1_RESET 0x8000 /* BMCR_RESET */
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#define MDIO_CTRL1_SPEEDSELEXT 0x2040 /* BMCR_SPEED1000|BMCR_SPEED100*/
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#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x3c)
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#define MDIO_AN_CTRL1_ENABLE 0x1000 /* BMCR_AUTOEN */
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#define MDIO_CTRL1_LPOWER 0x0800 /* BMCR_PDOWN */
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#define MDIO_AN_CTRL1_RESTART 0x0200 /* BMCR_STARTNEG */
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#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
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#define MDIO_STAT1 1 /* MII_BMSR */
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#define MDIO_STAT1_LSTATUS 0x0004 /* BMSR_LINK */
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#define MDIO_DEVID1 2 /* MII_PHYSID1 */
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#define MDIO_DEVID2 3 /* MII_PHYSID2 */
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#define MDIO_SPEED 4
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#define MDIO_DEVS1 5
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#define MDIO_DEVS2 6
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#define MDIO_CTRL2 0x07
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#define MDIO_PCS_CTRL2_10GBR 0x0000
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#define MDIO_PCS_CTRL2_10GBX 0x0001
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#define MDIO_PCS_CTRL2_TYPE 0x0003
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#define MDIO_AN_ADVERTISE 16
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#define MDIO_AN_LPA 19
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#define ETH_ALEN ETHER_ADDR_LEN
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#define ETH_HLEN ETHER_HDR_LEN
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#define ETH_FCS_LEN 4
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#define VLAN_HLEN ETHER_VLAN_ENCAP_LEN
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#define VLAN_NVID 4096
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#define VLAN_VID_MASK 0x0FFF
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#define CRC32_POLY_LE 0xedb88320
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#define ARRAY_SIZE(x) nitems(x)
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#define BITS_PER_LONG (sizeof(long) * CHAR_BIT)
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#define BITS_TO_LONGS(n) howmany((n), BITS_PER_LONG)
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#define BITMAP_LAST_WORD_MASK(n) (~0UL >> (BITS_PER_LONG - (n)))
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#define min_t(t, a, b) MIN((t)(a), (t)(b))
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#define max_t(t, a, b) MAX((t)(a), (t)(b))
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static inline void
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clear_bit(int pos, unsigned long *p)
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{
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atomic_clear_long(p, 1ul << pos);
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}
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static inline int
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test_bit(int pos, unsigned long *p)
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{
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unsigned long val;
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val = *p;
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return ((val & 1ul << pos) != 0);
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}
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static inline void
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set_bit(int pos, unsigned long *p)
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{
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atomic_set_long(p, 1ul << pos);
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}
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static inline int
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__ffsl(long mask)
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{
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return (ffsl(mask) - 1);
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}
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static inline int
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fls64(uint64_t mask)
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{
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return (flsll(mask));
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}
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static inline int
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get_bitmask_order(unsigned int count)
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{
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int order;
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order = fls(count);
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return (order); /* We could be slightly more clever with -1 here... */
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}
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static inline unsigned long
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find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset)
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{
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long mask;
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int offs;
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int bit;
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int pos;
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if (offset >= size)
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return (size);
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pos = offset / BITS_PER_LONG;
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offs = offset % BITS_PER_LONG;
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bit = BITS_PER_LONG * pos;
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addr += pos;
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if (offs) {
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mask = (*addr) & ~BITMAP_LAST_WORD_MASK(offs);
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if (mask)
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return (bit + __ffsl(mask));
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if (size - bit <= BITS_PER_LONG)
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return (size);
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bit += BITS_PER_LONG;
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addr++;
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}
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for (size -= bit; size >= BITS_PER_LONG;
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size -= BITS_PER_LONG, bit += BITS_PER_LONG, addr++) {
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if (*addr == 0)
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continue;
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return (bit + __ffsl(*addr));
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}
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if (size) {
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mask = (*addr) & BITMAP_LAST_WORD_MASK(size);
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if (mask)
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bit += __ffsl(mask);
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else
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bit += size;
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}
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return (bit);
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}
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static inline unsigned long
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find_first_bit(const unsigned long *addr, unsigned long size)
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{
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long mask;
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int bit;
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for (bit = 0; size >= BITS_PER_LONG;
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size -= BITS_PER_LONG, bit += BITS_PER_LONG, addr++) {
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if (*addr == 0)
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continue;
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return (bit + __ffsl(*addr));
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}
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if (size) {
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mask = (*addr) & BITMAP_LAST_WORD_MASK(size);
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if (mask)
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bit += __ffsl(mask);
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else
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bit += size;
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}
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return (bit);
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}
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#endif /* _XGBE_OSDEP_H_ */
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