286 lines
9.6 KiB
C
286 lines
9.6 KiB
C
/*-
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* Copyright (C) 2001 Eduardo Horvath.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
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*
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* $FreeBSD$
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*/
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#ifndef _IF_GEMVAR_H
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#define _IF_GEMVAR_H
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#include <sys/queue.h>
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#include <sys/callout.h>
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/*
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* Transmit descriptor list size. This is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet. This limit is not actually enforced (packets with
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* more segments can be sent, depending on the busdma backend); it
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* is however used as an estimate for the TX window size.
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*/
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#define GEM_NTXSEGS 16
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#define GEM_TXQUEUELEN 64
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#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
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#define GEM_MAXTXFREE (GEM_NTXDESC - 1)
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#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
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#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
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/*
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* Receive descriptor list size. We have one RX buffer per incoming
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* packet, so this logic is a little simpler.
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*/
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#define GEM_NRXDESC 256
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#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
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#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
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/*
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* How many ticks to wait until to retry on a RX descriptor that is
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* still owned by the hardware.
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*/
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#define GEM_RXOWN_TICKS (hz / 50)
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/*
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* Control structures are DMA'd to the GEM chip. We allocate them
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* in a single clump that maps to a single DMA segment to make
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* several things easier.
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*/
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struct gem_control_data {
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struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */
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struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */
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};
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#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
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#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
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#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
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/*
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* software state for transmit job mbufs (may be elements of mbuf chains)
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*/
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struct gem_txsoft {
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struct mbuf *txs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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int txs_firstdesc; /* first descriptor in packet */
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int txs_lastdesc; /* last descriptor in packet */
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int txs_ndescs; /* number of descriptors */
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STAILQ_ENTRY(gem_txsoft) txs_q;
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};
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STAILQ_HEAD(gem_txsq, gem_txsoft);
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/*
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* software state for receive jobs
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*/
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struct gem_rxsoft {
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struct mbuf *rxs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t rxs_dmamap; /* our DMA map */
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bus_addr_t rxs_paddr; /* physical address of the segment */
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};
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/*
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* software state per device
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*/
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struct gem_softc {
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struct ifnet *sc_ifp;
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struct mtx sc_mtx;
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device_t sc_miibus;
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struct mii_data *sc_mii; /* MII media control */
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device_t sc_dev; /* generic device information */
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u_char sc_enaddr[ETHER_ADDR_LEN];
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struct callout sc_tick_ch; /* tick callout */
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struct callout sc_rx_ch; /* delayed RX callout */
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int sc_wdog_timer; /* watchdog timer */
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void *sc_ih;
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struct resource *sc_res[3];
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#define GEM_RES_INTR 0
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#define GEM_RES_BANK1 1
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#define GEM_RES_BANK2 2
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bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */
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bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */
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bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */
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bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */
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bus_dmamap_t sc_dmamap; /* bus DMA handle */
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int sc_phyad; /* PHY to use or -1 for any */
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u_int sc_variant;
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#define GEM_UNKNOWN 0 /* don't know */
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#define GEM_SUN_GEM 1 /* Sun GEM */
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#define GEM_SUN_ERI 2 /* Sun ERI */
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#define GEM_APPLE_GMAC 3 /* Apple GMAC */
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#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
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#define GEM_IS_APPLE(sc) \
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((sc)->sc_variant == GEM_APPLE_GMAC || \
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(sc)->sc_variant == GEM_APPLE_K2_GMAC)
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u_int sc_flags;
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#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */
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#define GEM_LINK (1 << 1) /* link is up */
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#define GEM_PCI (1 << 2) /* PCI busses are little-endian */
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#define GEM_SERDES (1 << 3) /* use the SERDES */
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/*
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* ring buffer DMA stuff
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*/
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bus_dma_segment_t sc_cdseg; /* control data memory */
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int sc_cdnseg; /* number of segments */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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bus_addr_t sc_cddma;
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/*
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* software state for transmit and receive descriptors
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*/
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struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
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struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
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/*
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* control data structures
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*/
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struct gem_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->gcd_txdescs
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#define sc_rxdescs sc_control_data->gcd_rxdescs
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int sc_txfree; /* number of free TX descriptors */
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int sc_txnext; /* next ready TX descriptor */
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int sc_txwin; /* TX desc. since last TX intr. */
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struct gem_txsq sc_txfreeq; /* free TX descsofts */
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struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */
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int sc_rxptr; /* next ready RX desc./descsoft */
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int sc_rxfifosize; /* RX FIFO size (bytes) */
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int sc_ifflags;
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int sc_csum_features;
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};
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#define GEM_BANKN_BARRIER(n, sc, offs, len, flags) \
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bus_barrier((sc)->sc_res[(n)], (offs), (len), (flags))
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#define GEM_BANK1_BARRIER(sc, offs, len, flags) \
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GEM_BANKN_BARRIER(GEM_RES_BANK1, (sc), (offs), (len), (flags))
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#define GEM_BANK2_BARRIER(sc, offs, len, flags) \
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GEM_BANKN_BARRIER(GEM_RES_BANK2, (sc), (offs), (len), (flags))
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#define GEM_BANKN_READ_M(n, m, sc, offs) \
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bus_read_ ## m((sc)->sc_res[(n)], (offs))
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#define GEM_BANK1_READ_1(sc, offs) \
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GEM_BANKN_READ_M(GEM_RES_BANK1, 1, (sc), (offs))
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#define GEM_BANK1_READ_2(sc, offs) \
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GEM_BANKN_READ_M(GEM_RES_BANK1, 2, (sc), (offs))
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#define GEM_BANK1_READ_4(sc, offs) \
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GEM_BANKN_READ_M(GEM_RES_BANK1, 4, (sc), (offs))
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#define GEM_BANK2_READ_1(sc, offs) \
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GEM_BANKN_READ_M(GEM_RES_BANK2, 1, (sc), (offs))
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#define GEM_BANK2_READ_2(sc, offs) \
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GEM_BANKN_READ_M(GEM_RES_BANK2, 2, (sc), (offs))
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#define GEM_BANK2_READ_4(sc, offs) \
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GEM_BANKN_READ_M(GEM_RES_BANK2, 4, (sc), (offs))
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#define GEM_BANKN_WRITE_M(n, m, sc, offs, v) \
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bus_write_ ## m((sc)->sc_res[n], (offs), (v))
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#define GEM_BANK1_WRITE_1(sc, offs, v) \
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GEM_BANKN_WRITE_M(GEM_RES_BANK1, 1, (sc), (offs), (v))
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#define GEM_BANK1_WRITE_2(sc, offs, v) \
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GEM_BANKN_WRITE_M(GEM_RES_BANK1, 2, (sc), (offs), (v))
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#define GEM_BANK1_WRITE_4(sc, offs, v) \
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GEM_BANKN_WRITE_M(GEM_RES_BANK1, 4, (sc), (offs), (v))
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#define GEM_BANK2_WRITE_1(sc, offs, v) \
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GEM_BANKN_WRITE_M(GEM_RES_BANK2, 1, (sc), (offs), (v))
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#define GEM_BANK2_WRITE_2(sc, offs, v) \
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GEM_BANKN_WRITE_M(GEM_RES_BANK2, 2, (sc), (offs), (v))
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#define GEM_BANK2_WRITE_4(sc, offs, v) \
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GEM_BANKN_WRITE_M(GEM_RES_BANK2, 4, (sc), (offs), (v))
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/* XXX this should be handled by bus_dma(9). */
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#define GEM_DMA_READ(sc, v) \
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((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
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#define GEM_DMA_WRITE(sc, v) \
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((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v))
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#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
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#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
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#define GEM_CDSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
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#define GEM_INIT_RXDESC(sc, x) \
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do { \
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struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
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struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
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struct mbuf *__m = __rxs->rxs_mbuf; \
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\
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__m->m_data = __m->m_ext.ext_buf; \
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__rxd->gd_addr = \
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GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
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__rxd->gd_flags = \
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GEM_DMA_WRITE((sc), \
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(((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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} while (0)
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#define GEM_UPDATE_RXDESC(sc, x) \
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do { \
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struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
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struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
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struct mbuf *__m = __rxs->rxs_mbuf; \
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\
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__rxd->gd_flags = \
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GEM_DMA_WRITE((sc), \
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(((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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} while (0)
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#define GEM_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
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#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
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#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#ifdef _KERNEL
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extern devclass_t gem_devclass;
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int gem_attach(struct gem_softc *sc);
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void gem_detach(struct gem_softc *sc);
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void gem_intr(void *v);
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void gem_resume(struct gem_softc *sc);
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void gem_suspend(struct gem_softc *sc);
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int gem_mediachange(struct ifnet *ifp);
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void gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
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/* MII methods & callbacks */
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int gem_mii_readreg(device_t dev, int phy, int reg);
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void gem_mii_statchg(device_t dev);
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int gem_mii_writereg(device_t dev, int phy, int reg, int val);
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#endif /* _KERNEL */
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#endif
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