freebsd-skq/sys/mips/atheros
Marius Strobl 3fcb7a5365 - Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP
(reporting IFM_LOOP based on BMCR_LOOP is left in place though as
  it might provide useful for debugging). For most mii(4) drivers it
  was unclear whether the PHYs driven by them actually support
  loopback or not. Moreover, typically loopback mode also needs to
  be activated on the MAC, which none of the Ethernet drivers using
  mii(4) implements. Given that loopback media has no real use (and
  obviously hardly had a chance to actually work) besides for driver
  development (which just loopback mode should be sufficient for
  though, i.e one doesn't necessary need support for loopback media)
  support for it is just dropped as both NetBSD and OpenBSD already
  did quite some time ago.
- Let mii_phy_add_media() also announce the support of IFM_NONE.
- Restructure the PHY entry points to use a structure of entry points
  instead of discrete function pointers, and extend this to include
  a "reset" entry point. Make sure any PHY-specific reset routine is
  always used, and provide one for lxtphy(4) which disables MII
  interrupts (as is done for a few other PHYs we have drivers for).
  This includes changing NIC drivers which previously just called the
  generic mii_phy_reset() to now actually call the PHY-specific reset
  routine, which might be crucial in some cases. While at it, the
  redundant checks in these NIC drivers for mii->mii_instance not being
  zero before calling the reset routines were removed because as soon
  as one PHY driver attaches mii->mii_instance is incremented and we
  hardly can end up in their media change callbacks etc if no PHY driver
  has attached as mii_attach() would have failed in that case and not
  attach a miibus(4) instance.
  Consequently, NIC drivers now no longer should call mii_phy_reset()
  directly, so it was removed from EXPORT_SYMS.
- Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe().
  The purpose of that function is to perform the common steps to attach
  a PHY driver instance and to hook it up to the miibus(4) instance and to
  optionally also handle the probing, addition and initialization of the
  supported media. So all a PHY driver without any special requirements
  has to do in its bus attach method is to call mii_phy_dev_attach()
  along with PHY-specific MIIF_* flags, a pointer to its PHY functions
  and the add_media set to one. All PHY drivers were updated to take
  advantage of mii_phy_dev_attach() as appropriate. Along with these
  changes the capability mask was added to the mii_softc structure so
  PHY drivers taking advantage of mii_phy_dev_attach() but still
  handling media on their own do not need to fiddle with the MII attach
  arguments anyway.
- Keep track of the PHY offset in the mii_softc structure. This is done
  for compatibility with NetBSD/OpenBSD.
- Keep track of the PHY's OUI, model and revision in the mii_softc
  structure. Several PHY drivers require this information also after
  attaching and previously had to wrap their own softc around mii_softc.
  NetBSD/OpenBSD also keep track of the model and revision on their
  mii_softc structure. All PHY drivers were updated to take advantage
  as appropriate.
- Convert the mebers of the MII data structure to unsigned where
  appropriate. This is partly inspired by NetBSD/OpenBSD.
- According to IEEE 802.3-2002 the bits actually have to be reversed
  when mapping an OUI to the MII ID registers. All PHY drivers and
  miidevs where changed as necessary. Actually this now again allows to
  largely share miidevs with NetBSD, which fixed this problem already
  9 years ago. Consequently miidevs was synced as far as possible.
- Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that
  weren't explicitly converted to support flow control before. It's
  unclear whether flow control actually works with these but typically
  it should and their net behavior should be more correct with these
  changes in place than without if the MAC driver sets MIIF_DOPAUSE.

Obtained from:	NetBSD (partially)
Reviewed by:	yongari (earlier version), silence on arch@ and net@
2011-05-03 19:51:29 +00:00
..
apb.c The AR724x SoC's require the irq status line to be acked/cleared. 2011-04-30 12:07:15 +00:00
apbvar.h - Add intr counters for APB interrupts 2009-11-18 22:53:05 +00:00
ar71xx_bus_space_reversed.c - Handle byte-order issue for non-word accesses to memory mapped 2009-04-19 22:56:35 +00:00
ar71xx_bus_space_reversed.h - Handle byte-order issue for non-word accesses to memory mapped 2009-04-19 22:56:35 +00:00
ar71xx_chip.c Add a missing DDR FIFO method for the ar71xx. 2011-04-30 02:31:56 +00:00
ar71xx_chip.h Preparation work for supporting the AR91xx and AR724x. 2010-08-19 02:03:12 +00:00
ar71xx_cpudef.h Tidy up the naming of the ip2 DDR flush routine, and add an inline 2011-04-29 06:25:11 +00:00
ar71xx_ehci.c We don't need to call EOWRITE4(sc, EHCI_USBINTR, 0) directly from each EHCI 2011-04-12 07:49:11 +00:00
ar71xx_gpio.c - Fix values of CS1_EN and CS2_EN flags 2010-09-29 23:06:41 +00:00
ar71xx_gpiovar.h Add AR71XX GPIO bus driver. 2010-09-28 03:31:34 +00:00
ar71xx_machdep.c The previous commit didn't completely rename this to what it should be. 2011-03-28 09:10:59 +00:00
ar71xx_ohci.c - include register definitions for respective controllers 2009-11-12 20:48:04 +00:00
ar71xx_pci_bus_space.c - Add pci bus space that translates byte order to little endian, 2009-05-15 21:36:50 +00:00
ar71xx_pci_bus_space.h - Add pci bus space that translates byte order to little endian, 2009-05-15 21:36:50 +00:00
ar71xx_pci.c Call the DDR FIFO flush method when IP2 interrupts occur. 2011-04-30 11:56:04 +00:00
ar71xx_setup.c Fix mistaken indenting. 2010-08-19 12:52:49 +00:00
ar71xx_setup.h Preparation work for supporting the AR91xx and AR724x. 2010-08-19 02:03:12 +00:00
ar71xx_spi.c - Remove unnecessary register writes in activate_device 2010-01-21 00:15:59 +00:00
ar71xx_wdog.c Preparation work for supporting the AR91xx and AR724x. 2010-08-19 02:03:12 +00:00
ar71xxreg.h - Fix values of CS1_EN and CS2_EN flags 2010-09-29 23:06:41 +00:00
ar91xx_chip.c Add the IP2 DDR flush handlers. 2011-04-28 11:13:26 +00:00
ar91xx_chip.h Add initial Atheros AR91XX support. 2010-08-19 11:40:10 +00:00
ar91xxreg.h Add missing ar91xx definition for the WMAC reset control. 2011-01-09 06:17:46 +00:00
ar724x_chip.c Add the IP2 DDR flush handlers. 2011-04-28 11:13:26 +00:00
ar724x_chip.h Add some initial AR724X chipset support. 2010-08-19 11:53:55 +00:00
ar724x_pci.c Some AR724x PCIe fixes, which should wrap up the first round 2011-05-01 23:32:37 +00:00
ar724xreg.h Add some initial PCIe bridge support for the AR724x chipsets. 2011-04-30 11:36:16 +00:00
files.ar71xx Add some initial PCIe bridge support for the AR724x chipsets. 2011-04-30 11:36:16 +00:00
if_arge.c - Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP 2011-05-03 19:51:29 +00:00
if_argevar.h * Add some more debugging to if_arge 2011-04-05 06:33:35 +00:00
pcf2123_rtc.c - Add driver for PCF2123, SPI real time clock/calendar 2010-01-22 22:14:12 +00:00
pcf2123reg.h - Add driver for PCF2123, SPI real time clock/calendar 2010-01-22 22:14:12 +00:00
std.ar71xx Remove the 'machine mips' from DEFAULTS. Put the proper 'machine mips 2010-11-13 22:34:12 +00:00
uart_bus_ar71xx.c Preparation work for supporting the AR91xx and AR724x. 2010-08-19 02:03:12 +00:00
uart_cpu_ar71xx.c Preparation work for supporting the AR91xx and AR724x. 2010-08-19 02:03:12 +00:00