68c30b183a
Machine privilege level was specially designed to use in vendor's firmware or bootloader. We have implemented operation in machine mode in FreeBSD as part of understanding RISC-V ISA, but it is time to remove it. We now use BBL (Berkeley Boot Loader) -- standard RISC-V firmware, which provides operation in machine mode for us. We now use standard SBI calls to machine mode, instead of handmade 'syscalls'. o Remove HTIF bus. HTIF bus is now legacy and no longer exists in RISC-V specification. HTIF code still exists in Spike simulator, but BBL do not provide raw interface to it. Memory disk is only choice for now to have multiuser booted in Spike, until Spike has implemented more devices (e.g. Virtio, etc). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
195 lines
5.9 KiB
C
195 lines
5.9 KiB
C
/*-
|
|
* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
|
|
* All rights reserved.
|
|
*
|
|
* Portions of this software were developed by SRI International and the
|
|
* University of Cambridge Computer Laboratory under DARPA/AFRL contract
|
|
* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
|
|
*
|
|
* Portions of this software were developed by the University of Cambridge
|
|
* Computer Laboratory as part of the CTSRD Project, with support from the
|
|
* UK Higher Education Innovation Fund (HEIF).
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
|
|
#ifndef _MACHINE_RISCVREG_H_
|
|
#define _MACHINE_RISCVREG_H_
|
|
|
|
#define EXCP_SHIFT 0
|
|
#define EXCP_MASK (0xf << EXCP_SHIFT)
|
|
#define EXCP_MISALIGNED_FETCH 0
|
|
#define EXCP_FAULT_FETCH 1
|
|
#define EXCP_ILLEGAL_INSTRUCTION 2
|
|
#define EXCP_BREAKPOINT 3
|
|
#define EXCP_MISALIGNED_LOAD 4
|
|
#define EXCP_FAULT_LOAD 5
|
|
#define EXCP_MISALIGNED_STORE 6
|
|
#define EXCP_FAULT_STORE 7
|
|
#define EXCP_USER_ECALL 8
|
|
#define EXCP_SUPERVISOR_ECALL 9
|
|
#define EXCP_HYPERVISOR_ECALL 10
|
|
#define EXCP_MACHINE_ECALL 11
|
|
#define EXCP_INTR (1ul << 63)
|
|
|
|
#define SSTATUS_UIE (1 << 0)
|
|
#define SSTATUS_SIE (1 << 1)
|
|
#define SSTATUS_UPIE (1 << 4)
|
|
#define SSTATUS_SPIE (1 << 5)
|
|
#define SSTATUS_SPIE_SHIFT 5
|
|
#define SSTATUS_SPP (1 << 8)
|
|
#define SSTATUS_SPP_SHIFT 8
|
|
#define SSTATUS_FS_MASK 0x3
|
|
#define SSTATUS_FS_SHIFT 13
|
|
#define SSTATUS_XS_MASK 0x3
|
|
#define SSTATUS_XS_SHIFT 15
|
|
#define SSTATUS_PUM (1 << 18)
|
|
#define SSTATUS32_SD (1 << 63)
|
|
#define SSTATUS64_SD (1 << 31)
|
|
|
|
#define MSTATUS_UIE (1 << 0)
|
|
#define MSTATUS_SIE (1 << 1)
|
|
#define MSTATUS_HIE (1 << 2)
|
|
#define MSTATUS_MIE (1 << 3)
|
|
#define MSTATUS_UPIE (1 << 4)
|
|
#define MSTATUS_SPIE (1 << 5)
|
|
#define MSTATUS_SPIE_SHIFT 5
|
|
#define MSTATUS_HPIE (1 << 6)
|
|
#define MSTATUS_MPIE (1 << 7)
|
|
#define MSTATUS_MPIE_SHIFT 7
|
|
#define MSTATUS_SPP (1 << 8)
|
|
#define MSTATUS_SPP_SHIFT 8
|
|
#define MSTATUS_HPP_MASK 0x3
|
|
#define MSTATUS_HPP_SHIFT 9
|
|
#define MSTATUS_MPP_MASK 0x3
|
|
#define MSTATUS_MPP_SHIFT 11
|
|
#define MSTATUS_FS_MASK 0x3
|
|
#define MSTATUS_FS_SHIFT 13
|
|
#define MSTATUS_XS_MASK 0x3
|
|
#define MSTATUS_XS_SHIFT 15
|
|
#define MSTATUS_MPRV (1 << 17)
|
|
#define MSTATUS_PUM (1 << 18)
|
|
#define MSTATUS_VM_MASK 0x1f
|
|
#define MSTATUS_VM_SHIFT 24
|
|
#define MSTATUS_VM_MBARE 0
|
|
#define MSTATUS_VM_MBB 1
|
|
#define MSTATUS_VM_MBBID 2
|
|
#define MSTATUS_VM_SV32 8
|
|
#define MSTATUS_VM_SV39 9
|
|
#define MSTATUS_VM_SV48 10
|
|
#define MSTATUS_VM_SV57 11
|
|
#define MSTATUS_VM_SV64 12
|
|
#define MSTATUS32_SD (1 << 63)
|
|
#define MSTATUS64_SD (1 << 31)
|
|
|
|
#define MSTATUS_PRV_U 0 /* user */
|
|
#define MSTATUS_PRV_S 1 /* supervisor */
|
|
#define MSTATUS_PRV_H 2 /* hypervisor */
|
|
#define MSTATUS_PRV_M 3 /* machine */
|
|
|
|
#define MIE_USIE (1 << 0)
|
|
#define MIE_SSIE (1 << 1)
|
|
#define MIE_HSIE (1 << 2)
|
|
#define MIE_MSIE (1 << 3)
|
|
#define MIE_UTIE (1 << 4)
|
|
#define MIE_STIE (1 << 5)
|
|
#define MIE_HTIE (1 << 6)
|
|
#define MIE_MTIE (1 << 7)
|
|
|
|
#define MIP_USIP (1 << 0)
|
|
#define MIP_SSIP (1 << 1)
|
|
#define MIP_HSIP (1 << 2)
|
|
#define MIP_MSIP (1 << 3)
|
|
#define MIP_UTIP (1 << 4)
|
|
#define MIP_STIP (1 << 5)
|
|
#define MIP_HTIP (1 << 6)
|
|
#define MIP_MTIP (1 << 7)
|
|
|
|
#define SIE_USIE (1 << 0)
|
|
#define SIE_SSIE (1 << 1)
|
|
#define SIE_UTIE (1 << 4)
|
|
#define SIE_STIE (1 << 5)
|
|
|
|
#define MIP_SEIP (1 << 9)
|
|
|
|
/* Note: sip register has no SIP_STIP bit in Spike simulator */
|
|
#define SIP_SSIP (1 << 1)
|
|
#define SIP_STIP (1 << 5)
|
|
|
|
#if 0
|
|
/* lowRISC TODO */
|
|
#define NCSRS 4096
|
|
#define CSR_IPI 0x783
|
|
#define CSR_IO_IRQ 0x7c0 /* lowRISC only? */
|
|
#endif
|
|
|
|
#define XLEN 8
|
|
#define INSN_SIZE 4
|
|
|
|
#define RISCV_INSN_NOP 0x00000013
|
|
#define RISCV_INSN_BREAK 0x00100073
|
|
#define RISCV_INSN_RET 0x00008067
|
|
|
|
#define CSR_ZIMM(val) \
|
|
(__builtin_constant_p(val) && ((u_long)(val) < 32))
|
|
|
|
#define csr_swap(csr, val) \
|
|
({ if (CSR_ZIMM(val)) \
|
|
__asm __volatile("csrrwi %0, " #csr ", %1" \
|
|
: "=r" (val) : "i" (val)); \
|
|
else \
|
|
__asm __volatile("csrrw %0, " #csr ", %1" \
|
|
: "=r" (val) : "r" (val)); \
|
|
val; \
|
|
})
|
|
|
|
#define csr_write(csr, val) \
|
|
({ if (CSR_ZIMM(val)) \
|
|
__asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
|
|
else \
|
|
__asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
|
|
})
|
|
|
|
#define csr_set(csr, val) \
|
|
({ if (CSR_ZIMM(val)) \
|
|
__asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
|
|
else \
|
|
__asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
|
|
})
|
|
|
|
#define csr_clear(csr, val) \
|
|
({ if (CSR_ZIMM(val)) \
|
|
__asm __volatile("csrci " #csr ", %0" :: "i" (val)); \
|
|
else \
|
|
__asm __volatile("csrc " #csr ", %0" :: "r" (val)); \
|
|
})
|
|
|
|
#define csr_read(csr) \
|
|
({ u_long val; \
|
|
__asm __volatile("csrr %0, " #csr : "=r" (val)); \
|
|
val; \
|
|
})
|
|
|
|
#endif /* !_MACHINE_RISCVREG_H_ */
|