337 lines
12 KiB
C
337 lines
12 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TEGRA124_CAR_
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#define _TEGRA124_CAR_
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#include "clkdev_if.h"
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#define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val)
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#define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val)
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#define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set)
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#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
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#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
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#define RST_DEVICES_L 0x004
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#define RST_DEVICES_H 0x008
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#define RST_DEVICES_U 0x00C
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#define CLK_OUT_ENB_L 0x010
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#define CLK_OUT_ENB_H 0x014
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#define CLK_OUT_ENB_U 0x018
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#define CCLK_BURST_POLICY 0x020
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#define SUPER_CCLK_DIVIDER 0x024
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#define SCLK_BURST_POLICY 0x028
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#define SUPER_SCLK_DIVIDER 0x02c
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#define CLK_SYSTEM_RATE 0x030
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#define OSC_CTRL 0x050
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#define OSC_CTRL_OSC_FREQ_SHIFT 28
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#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
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#define PLLE_SS_CNTL 0x068
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#define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24)
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#define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24)
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#define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16)
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#define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16)
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#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
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#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
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#define PLLE_SS_CNTL_SSCBYP (1 << 12)
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#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
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#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
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#define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff
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#define PLLE_SS_CNTL_SSCMAX_VAL 0x25
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#define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \
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PLLE_SS_CNTL_INTERP_RESET | \
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PLLE_SS_CNTL_SSCBYP)
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#define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \
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PLLE_SS_CNTL_SSCINC_MASK | \
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PLLE_SS_CNTL_SSCINCINTRV_MASK)
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#define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \
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PLLE_SS_CNTL_SSCINC_VAL | \
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PLLE_SS_CNTL_SSCINCINTRV_VAL)
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#define PLLC_BASE 0x080
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#define PLLC_OUT 0x084
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#define PLLC_MISC2 0x088
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#define PLLC_MISC 0x08c
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#define PLLM_BASE 0x090
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#define PLLM_OUT 0x094
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#define PLLM_MISC 0x09c
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#define PLLP_BASE 0x0a0
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#define PLLP_MISC 0x0ac
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#define PLLP_OUTA 0x0a4
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#define PLLP_OUTB 0x0a8
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#define PLLA_BASE 0x0b0
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#define PLLA_OUT 0x0b4
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#define PLLA_MISC 0x0bc
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#define PLLU_BASE 0x0c0
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#define PLLU_MISC 0x0cc
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#define PLLD_BASE 0x0d0
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#define PLLD_MISC 0x0dc
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#define PLLX_BASE 0x0e0
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#define PLLX_MISC 0x0e4
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#define PLLE_BASE 0x0e8
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#define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
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#define PLLE_BASE_DIVCML_SHIFT 24
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#define PLLE_BASE_DIVCML_MASK 0xf
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#define PLLE_MISC 0x0ec
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#define PLLE_MISC_SETUP_BASE_SHIFT 16
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#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
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#define PLLE_MISC_READY (1 << 15)
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#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
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#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
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#define PLLE_MISC_LOCK (1 << 11)
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#define PLLE_MISC_REF_ENABLE (1 << 10)
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#define PLLE_MISC_LOCK_ENABLE (1 << 9)
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#define PLLE_MISC_PTS (1 << 8)
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#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
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#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
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#define PLLE_MISC_VREG_CTRL_SHIFT 2
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#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
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#define CLK_SOURCE_I2S1 0x100
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#define CLK_SOURCE_I2S2 0x104
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#define CLK_SOURCE_SPDIF_OUT 0x108
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#define CLK_SOURCE_SPDIF_IN 0x10c
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#define CLK_SOURCE_PWM 0x110
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#define CLK_SOURCE_SPI2 0x118
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#define CLK_SOURCE_SPI3 0x11c
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#define CLK_SOURCE_I2C1 0x124
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#define CLK_SOURCE_I2C5 0x128
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#define CLK_SOURCE_SPI1 0x134
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#define CLK_SOURCE_DISP1 0x138
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#define CLK_SOURCE_DISP2 0x13c
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#define CLK_SOURCE_ISP 0x144
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#define CLK_SOURCE_VI 0x148
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#define CLK_SOURCE_SDMMC1 0x150
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#define CLK_SOURCE_SDMMC2 0x154
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#define CLK_SOURCE_SDMMC4 0x164
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#define CLK_SOURCE_VFIR 0x168
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#define CLK_SOURCE_HSI 0x174
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#define CLK_SOURCE_UARTA 0x178
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#define CLK_SOURCE_UARTB 0x17c
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#define CLK_SOURCE_HOST1X 0x180
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#define CLK_SOURCE_HDMI 0x18c
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#define CLK_SOURCE_I2C2 0x198
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#define CLK_SOURCE_EMC 0x19c
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#define CLK_SOURCE_UARTC 0x1a0
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#define CLK_SOURCE_VI_SENSOR 0x1a8
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#define CLK_SOURCE_SPI4 0x1b4
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#define CLK_SOURCE_I2C3 0x1b8
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#define CLK_SOURCE_SDMMC3 0x1bc
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#define CLK_SOURCE_UARTD 0x1c0
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#define CLK_SOURCE_VDE 0x1c8
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#define CLK_SOURCE_OWR 0x1cc
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#define CLK_SOURCE_NOR 0x1d0
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#define CLK_SOURCE_CSITE 0x1d4
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#define CLK_SOURCE_I2S0 0x1d8
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#define CLK_SOURCE_DTV 0x1dc
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#define CLK_SOURCE_MSENC 0x1f0
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#define CLK_SOURCE_TSEC 0x1f4
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#define CLK_SOURCE_SPARE2 0x1f8
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#define CLK_OUT_ENB_X 0x280
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#define RST_DEVICES_X 0x28C
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#define RST_DEVICES_V 0x358
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#define RST_DEVICES_W 0x35C
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#define CLK_OUT_ENB_V 0x360
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#define CLK_OUT_ENB_W 0x364
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#define CCLKG_BURST_POLICY 0x368
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#define SUPER_CCLKG_DIVIDER 0x36C
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#define CCLKLP_BURST_POLICY 0x370
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#define SUPER_CCLKLP_DIVIDER 0x374
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#define CLK_SOURCE_MSELECT 0x3b4
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#define CLK_SOURCE_TSENSOR 0x3b8
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#define CLK_SOURCE_I2S3 0x3bc
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#define CLK_SOURCE_I2S4 0x3c0
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#define CLK_SOURCE_I2C4 0x3c4
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#define CLK_SOURCE_SPI5 0x3c8
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#define CLK_SOURCE_SPI6 0x3cc
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#define CLK_SOURCE_AUDIO 0x3d0
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#define CLK_SOURCE_DAM0 0x3d8
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#define CLK_SOURCE_DAM1 0x3dc
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#define CLK_SOURCE_DAM2 0x3e0
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#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
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#define CLK_SOURCE_ACTMON 0x3e8
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#define CLK_SOURCE_EXTPERIPH1 0x3ec
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#define CLK_SOURCE_EXTPERIPH2 0x3f0
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#define CLK_SOURCE_EXTPERIPH3 0x3f4
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#define CLK_SOURCE_I2C_SLOW 0x3fc
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#define CLK_SOURCE_SYS 0x400
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#define CLK_SOURCE_SOR0 0x414
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#define CLK_SOURCE_SATA_OOB 0x420
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#define CLK_SOURCE_SATA 0x424
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#define CLK_SOURCE_HDA 0x428
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#define UTMIP_PLL_CFG0 0x480
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#define UTMIP_PLL_CFG1 0x484
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#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
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#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
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#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
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#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
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#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
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#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
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#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
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#define UTMIP_PLL_CFG2 0x488
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#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
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#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
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#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
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#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
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#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
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#define PLLE_AUX 0x48c
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#define PLLE_AUX_PLLRE_SEL (1 << 28)
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#define PLLE_AUX_SEQ_START_STATE (1 << 25)
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#define PLLE_AUX_SEQ_ENABLE (1 << 24)
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#define PLLE_AUX_SS_SWCTL (1 << 6)
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#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
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#define PLLE_AUX_USE_LOCKDET (1 << 3)
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#define PLLE_AUX_PLLP_SEL (1 << 2)
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#define SATA_PLL_CFG0 0x490
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#define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25)
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#define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24)
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#define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7)
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#define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6)
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#define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5)
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#define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4)
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#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2)
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#define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1)
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#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
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#define SATA_PLL_CFG1 0x494
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#define PCIE_PLL_CFG0 0x498
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#define PCIE_PLL_CFG0_SEQ_START_STATE (1 << 25)
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#define PCIE_PLL_CFG0_SEQ_ENABLE (1 << 24)
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#define PLLD2_BASE 0x4b8
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#define PLLD2_MISC 0x4bc
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#define UTMIP_PLL_CFG3 0x4c0
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#define PLLRE_BASE 0x4c4
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#define PLLRE_MISC 0x4c8
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#define PLLC2_BASE 0x4e8
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#define PLLC2_MISC 0x4ec
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#define PLLC3_BASE 0x4fc
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#define PLLC3_MISC 0x500
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#define PLLX_MISC2 0x514
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#define PLLX_MISC2 0x514
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#define PLLX_MISC3 0x518
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#define PLLX_MISC3_DYNRAMP_STEPB_MASK 0xFF
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#define PLLX_MISC3_DYNRAMP_STEPB_SHIFT 24
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#define PLLX_MISC3_DYNRAMP_STEPA_MASK 0xFF
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#define PLLX_MISC3_DYNRAMP_STEPA_SHIFT 16
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#define PLLX_MISC3_NDIV_NEW_MASK 0xFF
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#define PLLX_MISC3_NDIV_NEW_SHIFT 8
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#define PLLX_MISC3_EN_FSTLCK (1 << 5)
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#define PLLX_MISC3_LOCK_OVERRIDE (1 << 4)
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#define PLLX_MISC3_PLL_FREQLOCK (1 << 3)
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#define PLLX_MISC3_DYNRAMP_DONE (1 << 2)
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#define PLLX_MISC3_CLAMP_NDIV (1 << 1)
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#define PLLX_MISC3_EN_DYNRAMP (1 << 0)
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#define XUSBIO_PLL_CFG0 0x51c
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#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25)
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#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
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#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
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#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
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#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
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#define PLLP_RESHIFT 0x528
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#define UTMIPLL_HW_PWRDN_CFG0 0x52c
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#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25)
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#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24)
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#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6)
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#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5)
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#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4)
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#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2)
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#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1)
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#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0)
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#define PLLDP_BASE 0x590
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#define PLLDP_MISC 0x594
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#define PLLC4_BASE 0x5a4
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#define PLLC4_MISC 0x5a8
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#define CLK_SOURCE_XUSB_CORE_HOST 0x600
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#define CLK_SOURCE_XUSB_FALCON 0x604
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#define CLK_SOURCE_XUSB_FS 0x608
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#define CLK_SOURCE_XUSB_CORE_DEV 0x60c
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#define CLK_SOURCE_XUSB_SS 0x610
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#define CLK_SOURCE_CILAB 0x614
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#define CLK_SOURCE_CILCD 0x618
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#define CLK_SOURCE_CILE 0x61c
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#define CLK_SOURCE_DSIA_LP 0x620
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#define CLK_SOURCE_DSIB_LP 0x624
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#define CLK_SOURCE_ENTROPY 0x628
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#define CLK_SOURCE_DVFS_REF 0x62c
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#define CLK_SOURCE_DVFS_SOC 0x630
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#define CLK_SOURCE_TRACECLKIN 0x634
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#define CLK_SOURCE_ADX 0x638
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#define CLK_SOURCE_AMX 0x63c
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#define CLK_SOURCE_EMC_LATENCY 0x640
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#define CLK_SOURCE_SOC_THERM 0x644
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#define CLK_SOURCE_VI_SENSOR2 0x658
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#define CLK_SOURCE_I2C6 0x65c
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#define CLK_SOURCE_EMC_DLL 0x664
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#define CLK_SOURCE_HDMI_AUDIO 0x668
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#define CLK_SOURCE_CLK72MHZ 0x66c
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#define CLK_SOURCE_ADX1 0x670
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#define CLK_SOURCE_AMX1 0x674
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#define CLK_SOURCE_VIC 0x678
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#define PLLP_OUTC 0x67c
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#define PLLP_MISC1 0x680
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struct tegra124_car_softc {
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device_t dev;
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struct resource * mem_res;
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struct mtx mtx;
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struct clkdom *clkdom;
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int type;
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};
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struct tegra124_init_item {
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char *name;
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char *parent;
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uint64_t frequency;
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int enable;
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};
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void tegra124_init_plls(struct tegra124_car_softc *sc);
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void tegra124_periph_clock(struct tegra124_car_softc *sc);
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void tegra124_super_mux_clock(struct tegra124_car_softc *sc);
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int tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx,
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bool reset);
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#endif /*_TEGRA124_CAR_*/
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