4d8ea19f7c
Some have dual host->PCI bridges for the same logical pci bus (!), eg: some of the RCC chipsets. This is a 32/64 bit 33/66MHz and dual pci voltage motherboard so persumably there are electical or signalling differences but they are otherwise the same logical bus. The new PCI probe code however was getting somewhat upset about it and ended up creating two pci bridges to the same logical bus, which caused devices on that logical bus to appear and be probed twice. The ACPI data on this box correctly identifies this stuff, so bring on ACPI! :-)
858 lines
20 KiB
C
858 lines
20 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <i386/isa/pcibus.h>
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#include <isa/isavar.h>
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#include <machine/segments.h>
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#include <machine/pc/bios.h>
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#include "pcib_if.h"
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int pcibios_cfgread(int bus, int slot, int func, int reg,
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int bytes);
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static void pcibios_cfgwrite(int bus, int slot, int func, int reg,
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int data, int bytes);
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(int bus, int slot, int func, int reg,
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int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg,
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int data, int bytes);
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static int pcireg_cfgopen(void);
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/* read configuration space register */
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static int
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nexus_pcib_maxslots(device_t dev)
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{
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return 31;
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}
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static u_int32_t
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nexus_pcib_read_config(device_t dev, int bus, int slot, int func,
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int reg, int bytes)
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{
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return(usebios ?
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pcibios_cfgread(bus, slot, func, reg, bytes) :
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pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/* write configuration space register */
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static void
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nexus_pcib_write_config(device_t dev, int bus, int slot, int func,
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int reg, u_int32_t data, int bytes)
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{
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return(usebios ?
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pcibios_cfgwrite(bus, slot, func, reg, data, bytes) :
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes));
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}
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/* initialise access to PCI configuration space */
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static int
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pci_cfgopen(void)
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{
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if (pcibios_cfgopen() != 0) {
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usebios = 1;
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} else if (pcireg_cfgopen() != 0) {
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usebios = 0;
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} else {
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return(0);
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}
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return(1);
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}
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/* config space access using BIOS functions */
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static int
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pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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struct bios_regs args;
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u_int mask;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_READ_CONFIG_BYTE;
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mask = 0xff;
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break;
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case 2:
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args.eax = PCIBIOS_READ_CONFIG_WORD;
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mask = 0xffff;
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break;
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case 4:
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args.eax = PCIBIOS_READ_CONFIG_DWORD;
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mask = 0xffffffff;
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break;
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default:
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return(-1);
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}
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args.ebx = (bus << 8) | (slot << 3) | func;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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/* check call results? */
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return(args.ecx & mask);
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}
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static void
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pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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struct bios_regs args;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_WRITE_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
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break;
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default:
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return;
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}
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args.ebx = (bus << 8) | (slot << 3) | func;
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args.ecx = data;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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/* determine whether there is a PCI BIOS present */
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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}
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/* configuration space access using direct register operations */
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX
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&& slot < devmax
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&& func <= PCI_FUNCMAX
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&& reg <= PCI_REGMAX
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&& bytes != 3
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&& (unsigned) bytes <= 4
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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break;
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}
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0);
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outb(CONF2_FORWARD_PORT, 0);
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break;
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}
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}
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static int
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pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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int data = -1;
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int port;
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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return (data);
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}
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static void
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pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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}
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/* check whether the configuration mechanism has been correct identified */
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static int
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pci_cfgcheck(int maxdev)
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{
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u_char device;
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if (bootverbose)
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printf("pci_cfgcheck:\tdevice ");
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for (device = 0; device < maxdev; device++) {
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unsigned id, class, header;
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if (bootverbose)
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printf("%d ", device);
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id = inl(pci_cfgenable(0, device, 0, 0, 4));
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if (id == 0 || id == -1)
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continue;
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class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
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if (bootverbose)
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printf("[class=%06x] ", class);
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if (class == 0 || (class & 0xf870ff) != 0)
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continue;
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header = inb(pci_cfgenable(0, device, 0, 14, 1));
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if (bootverbose)
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printf("[hdr=%02x] ", header);
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if ((header & 0x7e) != 0)
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continue;
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if (bootverbose)
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printf("is there (id=%08x)\n", id);
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pci_cfgdisable();
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return (1);
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}
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if (bootverbose)
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printf("-- nothing found\n");
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pci_cfgdisable();
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return (0);
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}
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static int
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pcireg_cfgopen(void)
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{
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unsigned long mode1res,oldval1;
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unsigned char mode2res,oldval2;
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = 1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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outb(CONF1_ADDR_PORT +3, 0);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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}
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
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oldval2);
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}
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = 2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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mode2res = inb(CONF2_ENABLE_PORT);
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outb(CONF2_ENABLE_PORT, oldval2);
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if (bootverbose)
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printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
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mode2res, CONF2_ENABLE_CHK);
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if (mode2res == CONF2_ENABLE_RES) {
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if (bootverbose)
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printf("pci_open(2a):\tnow trying mechanism 2\n");
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if (pci_cfgcheck(16))
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return (cfgmech);
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}
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}
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cfgmech = 0;
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devmax = 0;
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return (cfgmech);
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}
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static devclass_t pcib_devclass;
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static const char *
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nexus_pcib_is_host_bridge(int bus, int slot, int func,
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u_int32_t id, u_int8_t class, u_int8_t subclass,
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u_int8_t *busnum)
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{
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const char *s = NULL;
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static u_int8_t pxb[4]; /* hack for 450nx */
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*busnum = 0;
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switch (id) {
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case 0x12258086:
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s = "Intel 824?? host to PCI bridge";
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/* XXX This is a guess */
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/* *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x41, 1); */
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*busnum = bus;
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break;
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case 0x71208086:
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s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
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break;
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case 0x71228086:
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s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
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break;
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case 0x71248086:
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s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
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break;
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case 0x71808086:
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s = "Intel 82443LX (440 LX) host to PCI bridge";
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break;
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case 0x71908086:
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s = "Intel 82443BX (440 BX) host to PCI bridge";
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break;
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case 0x71928086:
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s = "Intel 82443BX host to PCI bridge (AGP disabled)";
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break;
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case 0x71948086:
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s = "Intel 82443MX host to PCI bridge";
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break;
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case 0x71a08086:
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s = "Intel 82443GX host to PCI bridge";
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break;
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case 0x71a18086:
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s = "Intel 82443GX host to AGP bridge";
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break;
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case 0x71a28086:
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s = "Intel 82443GX host to PCI bridge (AGP disabled)";
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break;
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case 0x84c48086:
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s = "Intel 82454KX/GX (Orion) host to PCI bridge";
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*busnum = nexus_pcib_read_config(0, bus, slot, func, 0x4a, 1);
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break;
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case 0x84ca8086:
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/*
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* For the 450nx chipset, there is a whole bundle of
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* things pretending to be host bridges. The MIOC will
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* be seen first and isn't really a pci bridge (the
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* actual busses are attached to the PXB's). We need to
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* read the registers of the MIOC to figure out the
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* bus numbers for the PXB channels.
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*
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* Since the MIOC doesn't have a pci bus attached, we
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* pretend it wasn't there.
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*/
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pxb[0] = nexus_pcib_read_config(0, bus, slot, func,
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0xd0, 1); /* BUSNO[0] */
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pxb[1] = nexus_pcib_read_config(0, bus, slot, func,
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0xd1, 1) + 1; /* SUBA[0]+1 */
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pxb[2] = nexus_pcib_read_config(0, bus, slot, func,
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0xd3, 1); /* BUSNO[1] */
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pxb[3] = nexus_pcib_read_config(0, bus, slot, func,
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0xd4, 1) + 1; /* SUBA[1]+1 */
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return NULL;
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case 0x84cb8086:
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switch (slot) {
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case 0x12:
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s = "Intel 82454NX PXB#0, Bus#A";
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*busnum = pxb[0];
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break;
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case 0x13:
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s = "Intel 82454NX PXB#0, Bus#B";
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*busnum = pxb[1];
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break;
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case 0x14:
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s = "Intel 82454NX PXB#1, Bus#A";
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*busnum = pxb[2];
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break;
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case 0x15:
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s = "Intel 82454NX PXB#1, Bus#B";
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*busnum = pxb[3];
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break;
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}
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break;
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/* AMD -- vendor 0x1022 */
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case 0x70061022:
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s = "AMD-751 host to PCI bridge";
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break;
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/* SiS -- vendor 0x1039 */
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case 0x04961039:
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s = "SiS 85c496";
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break;
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case 0x04061039:
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s = "SiS 85c501";
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break;
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case 0x06011039:
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s = "SiS 85c601";
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break;
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case 0x55911039:
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s = "SiS 5591 host to PCI bridge";
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break;
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case 0x00011039:
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s = "SiS 5591 host to AGP bridge";
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break;
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/* VLSI -- vendor 0x1004 */
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case 0x00051004:
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s = "VLSI 82C592 Host to PCI bridge";
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break;
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/* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
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/* totally. Please let me know if anything wrong. -F */
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/* XXX need info on the MVP3 -- any takers? */
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case 0x05981106:
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s = "VIA 82C598MVP (Apollo MVP3) host bridge";
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break;
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/* AcerLabs -- vendor 0x10b9 */
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/* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
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/* id is '10b9" but the register always shows "10b9". -Foxfair */
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case 0x154110b9:
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s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
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break;
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/* OPTi -- vendor 0x1045 */
|
|
case 0xc7011045:
|
|
s = "OPTi 82C700 host to PCI bridge";
|
|
break;
|
|
case 0xc8221045:
|
|
s = "OPTi 82C822 host to PCI Bridge";
|
|
break;
|
|
|
|
/* RCC -- vendor 0x1166 */
|
|
case 0x00051166:
|
|
s = "RCC HE host to PCI bridge";
|
|
*busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
|
|
break;
|
|
|
|
case 0x00061166:
|
|
/* FALLTHROUGH */
|
|
case 0x00081166:
|
|
s = "RCC host to PCI bridge";
|
|
*busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
|
|
break;
|
|
|
|
case 0x00091166:
|
|
s = "RCC LE host to PCI bridge";
|
|
*busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
|
|
break;
|
|
|
|
/* Integrated Micro Solutions -- vendor 0x10e0 */
|
|
case 0x884910e0:
|
|
s = "Integrated Micro Solutions VL Bridge";
|
|
break;
|
|
|
|
default:
|
|
if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
|
|
s = "Host to PCI bridge";
|
|
break;
|
|
}
|
|
|
|
return s;
|
|
}
|
|
|
|
/*
|
|
* Scan the first pci bus for host-pci bridges and add pcib instances
|
|
* to the nexus for each bridge.
|
|
*/
|
|
static void
|
|
nexus_pcib_identify(driver_t *driver, device_t parent)
|
|
{
|
|
int bus, slot, func;
|
|
u_int8_t hdrtype;
|
|
int found = 0;
|
|
int pcifunchigh;
|
|
int found824xx = 0;
|
|
device_t child;
|
|
int *ivar;
|
|
|
|
if (pci_cfgopen() == 0)
|
|
return;
|
|
bus = 0;
|
|
retry:
|
|
for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
|
|
func = 0;
|
|
hdrtype = nexus_pcib_read_config(0, bus, slot, func,
|
|
PCIR_HEADERTYPE, 1);
|
|
if (hdrtype & PCIM_MFDEV)
|
|
pcifunchigh = 7;
|
|
else
|
|
pcifunchigh = 0;
|
|
for (func = 0; func <= pcifunchigh; func++) {
|
|
/*
|
|
* Read the IDs and class from the device.
|
|
*/
|
|
u_int32_t id;
|
|
u_int8_t class, subclass, busnum;
|
|
const char *s;
|
|
device_t *devs;
|
|
int ndevs, i;
|
|
|
|
id = nexus_pcib_read_config(0, bus, slot, func,
|
|
PCIR_DEVVENDOR, 4);
|
|
if (id == -1)
|
|
continue;
|
|
class = nexus_pcib_read_config(0, bus, slot, func,
|
|
PCIR_CLASS, 1);
|
|
subclass = nexus_pcib_read_config(0, bus, slot, func,
|
|
PCIR_SUBCLASS, 1);
|
|
|
|
s = nexus_pcib_is_host_bridge(bus, slot, func,
|
|
id, class, subclass,
|
|
&busnum);
|
|
if (s == NULL)
|
|
continue;
|
|
|
|
/*
|
|
* Check to see if the physical bus has already
|
|
* been seen. Eg: hybrid 32 and 64 bit host
|
|
* bridges to the same logical bus.
|
|
*/
|
|
if (device_get_children(parent, &devs, &ndevs) == 0) {
|
|
for (i = 0; s != NULL && i < ndevs; i++) {
|
|
if (strcmp(device_get_name(devs[i]),
|
|
"pcib") != 0)
|
|
continue;
|
|
ivar = device_get_ivars(devs[i]);
|
|
if (ivar == NULL)
|
|
continue;
|
|
if (busnum == *ivar)
|
|
s = NULL;
|
|
}
|
|
free(devs, M_TEMP);
|
|
}
|
|
|
|
if (s == NULL)
|
|
continue;
|
|
/*
|
|
* Add at priority 100 to make sure we
|
|
* go after any motherboard resources
|
|
*/
|
|
child = BUS_ADD_CHILD(parent, 100,
|
|
"pcib", busnum);
|
|
device_set_desc(child, s);
|
|
|
|
ivar = malloc(sizeof ivar[0], M_DEVBUF,
|
|
M_NOWAIT);
|
|
if (ivar == NULL)
|
|
panic("out of memory");
|
|
device_set_ivars(child, ivar);
|
|
ivar[0] = busnum;
|
|
|
|
found = 1;
|
|
if (id == 0x12258086)
|
|
found824xx = 1;
|
|
}
|
|
}
|
|
if (found824xx && bus == 0) {
|
|
bus++;
|
|
goto retry;
|
|
}
|
|
|
|
/*
|
|
* Make sure we add at least one bridge since some old
|
|
* hardware doesn't actually have a host-pci bridge device.
|
|
* Note that pci_cfgopen() thinks we have PCI devices..
|
|
*/
|
|
if (!found) {
|
|
if (bootverbose)
|
|
printf(
|
|
"nexus_pcib_identify: no bridge found, adding pcib0 anyway\n");
|
|
child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
|
|
ivar = malloc(sizeof ivar[0], M_DEVBUF, M_NOWAIT);
|
|
if (ivar == NULL)
|
|
panic("out of memory");
|
|
device_set_ivars(child, ivar);
|
|
ivar[0] = 0;
|
|
}
|
|
}
|
|
|
|
static int
|
|
nexus_pcib_probe(device_t dev)
|
|
{
|
|
|
|
if (pci_cfgopen() != 0)
|
|
return 0;
|
|
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
nexus_pcib_attach(device_t dev)
|
|
{
|
|
device_t child;
|
|
|
|
child = device_add_child(dev, "pci", device_get_unit(dev));
|
|
|
|
return bus_generic_attach(dev);
|
|
}
|
|
|
|
static int
|
|
nexus_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
|
{
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
*result = *(int*) device_get_ivars(dev);
|
|
return 0;
|
|
}
|
|
return ENOENT;
|
|
}
|
|
|
|
static int
|
|
nexus_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
|
|
{
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
*(int*) device_get_ivars(dev) = value;
|
|
return 0;
|
|
}
|
|
return ENOENT;
|
|
}
|
|
|
|
|
|
static device_method_t nexus_pcib_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_identify, nexus_pcib_identify),
|
|
DEVMETHOD(device_probe, nexus_pcib_probe),
|
|
DEVMETHOD(device_attach, nexus_pcib_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, nexus_pcib_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, nexus_pcib_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, nexus_pcib_maxslots),
|
|
DEVMETHOD(pcib_read_config, nexus_pcib_read_config),
|
|
DEVMETHOD(pcib_write_config, nexus_pcib_write_config),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t nexus_pcib_driver = {
|
|
"pcib",
|
|
nexus_pcib_methods,
|
|
1,
|
|
};
|
|
|
|
DRIVER_MODULE(pcib, nexus, nexus_pcib_driver, pcib_devclass, 0, 0);
|
|
|
|
|
|
/*
|
|
* Provide a device to "eat" the host->pci bridges that we dug up above
|
|
* and stop them showing up twice on the probes. This also stops them
|
|
* showing up as 'none' in pciconf -l.
|
|
*/
|
|
static int
|
|
pci_hostb_probe(device_t dev)
|
|
{
|
|
|
|
if (pci_get_class(dev) == PCIC_BRIDGE &&
|
|
pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
|
|
device_set_desc(dev, "Host to PCI bridge");
|
|
device_quiet(dev);
|
|
return 0;
|
|
}
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
pci_hostb_attach(device_t dev)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
static device_method_t pci_hostb_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, pci_hostb_probe),
|
|
DEVMETHOD(device_attach, pci_hostb_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
static driver_t pci_hostb_driver = {
|
|
"hostb",
|
|
pci_hostb_methods,
|
|
1,
|
|
};
|
|
static devclass_t pci_hostb_devclass;
|
|
|
|
DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
|
|
|
|
|
|
/*
|
|
* Install placeholder to claim the resources owned by the
|
|
* PCI bus interface. This could be used to extract the
|
|
* config space registers in the extreme case where the PnP
|
|
* ID is available and the PCI BIOS isn't, but for now we just
|
|
* eat the PnP ID and do nothing else.
|
|
*
|
|
* XXX we should silence this probe, as it will generally confuse
|
|
* people.
|
|
*/
|
|
static struct isa_pnp_id pcibus_pnp_ids[] = {
|
|
{ 0x030ad041 /* PNP030A */, "PCI Bus" },
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
pcibus_pnp_probe(device_t dev)
|
|
{
|
|
int result;
|
|
|
|
if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
|
|
device_quiet(dev);
|
|
return(result);
|
|
}
|
|
|
|
static int
|
|
pcibus_pnp_attach(device_t dev)
|
|
{
|
|
return(0);
|
|
}
|
|
|
|
static device_method_t pcibus_pnp_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, pcibus_pnp_probe),
|
|
DEVMETHOD(device_attach, pcibus_pnp_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t pcibus_pnp_driver = {
|
|
"pcibus_pnp",
|
|
pcibus_pnp_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t pcibus_pnp_devclass;
|
|
|
|
DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
|