ae09eb7337
- Disable the support for the second channel on twin-channel EISA cards as the current incarnation can't possibly work correctly (it hasn't worked since switching to new-bus where new-bus allocates the softc). If anyone bothers to test this again it can be fixed properly and brought back. - Use device_printf() and device_get_nameunit() instead of adv_name(). - Remove use of explicit bus space handles and tags. - Use PCI bus accessors and helper routines rather than accessing config registers directly. - Handle failures from adv_attach(). Tested by: no one (hope it works)
331 lines
9.4 KiB
C
331 lines
9.4 KiB
C
/*-
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* Device probe and attach routines for the following
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* Advanced Systems Inc. SCSI controllers:
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*
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* Connectivity Products:
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* ABP902/3902 - Bus-Master PCI (16 CDB)
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* ABP3905 - Bus-Master PCI (16 CDB)
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* ABP915 - Bus-Master PCI (16 CDB)
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* ABP920 - Bus-Master PCI (16 CDB)
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* ABP3922 - Bus-Master PCI (16 CDB)
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* ABP3925 - Bus-Master PCI (16 CDB)
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* ABP930 - Bus-Master PCI (16 CDB) *
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* ABP930U - Bus-Master PCI Ultra (16 CDB)
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* ABP930UA - Bus-Master PCI Ultra (16 CDB)
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* ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
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* ABP960U - Bus-Master PCI MAC/PC (16 CDB) **
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*
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* Single Channel Products:
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* ABP940 - Bus-Master PCI (240 CDB)
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* ABP940U - Bus-Master PCI Ultra (240 CDB)
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* ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
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* ABP3960UA - Bus-Master PCI MAC/PC (240 CDB)
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* ABP970 - Bus-Master PCI MAC/PC (240 CDB)
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* ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
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*
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* Dual Channel Products:
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* ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
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* ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
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* ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
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* ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
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*
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* Footnotes:
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* * This board has been sold by SIIG as the Fast SCSI Pro PCI.
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* ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
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*
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* Copyright (c) 1997 Justin Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/advansys/advansys.h>
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#define PCI_BASEADR0 PCIR_BAR(0) /* I/O Address */
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#define PCI_BASEADR1 PCIR_BAR(1) /* Mem I/O Address */
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#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
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#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
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#define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD
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#define PCI_DEVICE_REV_ADVANSYS_3150 0x02
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#define PCI_DEVICE_REV_ADVANSYS_3050 0x03
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#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
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#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
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static int adv_pci_probe(device_t);
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static int adv_pci_attach(device_t);
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/*
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* The overrun buffer shared amongst all PCI adapters.
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*/
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static void* overrun_buf;
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static bus_dma_tag_t overrun_dmat;
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static bus_dmamap_t overrun_dmamap;
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static bus_addr_t overrun_physbase;
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static int
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adv_pci_probe(device_t dev)
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{
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int rev = pci_get_revid(dev);
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switch (pci_get_devid(dev)) {
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case PCI_DEVICE_ID_ADVANSYS_1200A:
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device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
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return BUS_PROBE_DEFAULT;
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case PCI_DEVICE_ID_ADVANSYS_1200B:
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device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
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return BUS_PROBE_DEFAULT;
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case PCI_DEVICE_ID_ADVANSYS_3000:
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if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
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device_set_desc(dev,
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"AdvanSys ASC3150 SCSI controller");
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return BUS_PROBE_DEFAULT;
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} else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
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device_set_desc(dev,
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"AdvanSys ASC3030/50 SCSI controller");
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return BUS_PROBE_DEFAULT;
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} else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
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device_set_desc(dev, "Unknown AdvanSys controller");
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return BUS_PROBE_DEFAULT;
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}
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break;
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default:
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break;
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}
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return ENXIO;
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}
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static int
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adv_pci_attach(device_t dev)
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{
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struct adv_softc *adv;
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u_int32_t id;
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int error, rid, irqrid;
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void *ih;
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struct resource *iores, *irqres;
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/*
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* Determine the chip version.
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*/
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id = pci_get_devid(dev);
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pci_enable_busmaster(dev);
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/*
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* Early chips can't handle non-zero latency timer settings.
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*/
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if (id == PCI_DEVICE_ID_ADVANSYS_1200A
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|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
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pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
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}
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rid = PCI_BASEADR0;
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iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
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RF_ACTIVE);
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if (iores == NULL)
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return ENXIO;
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if (adv_find_signature(iores) == 0) {
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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adv = adv_alloc(dev, iores, 0);
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if (adv == NULL) {
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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/* Allocate a dmatag for our transfer DMA maps */
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error = bus_dma_tag_create(
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/* parent */ bus_get_dma_tag(dev),
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/* alignment */ 1,
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/* boundary */ 0,
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/* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
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/* highaddr */ BUS_SPACE_MAXADDR,
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/* filter */ NULL,
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/* filterarg */ NULL,
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/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
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/* nsegments */ ~0,
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/* maxsegsz */ ADV_PCI_MAX_DMA_COUNT,
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/* flags */ 0,
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/* lockfunc */ NULL,
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/* lockarg */ NULL,
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&adv->parent_dmat);
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if (error != 0) {
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device_printf(dev, "Could not allocate DMA tag - error %d\n",
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error);
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adv_free(adv);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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adv->init_level++;
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if (overrun_buf == NULL) {
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/* Need to allocate our overrun buffer */
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if (bus_dma_tag_create(
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/* parent */ adv->parent_dmat,
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/* alignment */ 8,
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/* boundary */ 0,
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/* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
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/* highaddr */ BUS_SPACE_MAXADDR,
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/* filter */ NULL,
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/* filterarg */ NULL,
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/* maxsize */ ADV_OVERRUN_BSIZE,
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/* nsegments */ 1,
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/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
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/* flags */ 0,
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/* lockfunc */ NULL,
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/* lockarg */ NULL,
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&overrun_dmat) != 0) {
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bus_dma_tag_destroy(adv->parent_dmat);
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adv_free(adv);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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if (bus_dmamem_alloc(overrun_dmat,
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&overrun_buf,
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BUS_DMA_NOWAIT,
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&overrun_dmamap) != 0) {
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bus_dma_tag_destroy(overrun_dmat);
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bus_dma_tag_destroy(adv->parent_dmat);
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adv_free(adv);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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/* And permanently map it in */
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bus_dmamap_load(overrun_dmat, overrun_dmamap,
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overrun_buf, ADV_OVERRUN_BSIZE,
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adv_map, &overrun_physbase,
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/*flags*/0);
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}
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adv->overrun_physbase = overrun_physbase;
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/*
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* Stop the chip.
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*/
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ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
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ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
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adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
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adv->type = ADV_PCI;
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/*
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* Setup active negation and signal filtering.
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*/
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{
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u_int8_t extra_cfg;
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if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
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adv->type |= ADV_ULTRA;
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if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
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extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
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else
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extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
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ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
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}
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if (adv_init(adv) != 0) {
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adv_free(adv);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
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adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
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#if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT
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{
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u_int16_t config_msw;
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config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
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config_msw &= 0xFFC0;
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ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
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}
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#endif
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if (id == PCI_DEVICE_ID_ADVANSYS_1200A
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|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
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adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
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adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
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adv->fix_asyn_xfer = ~0;
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}
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irqrid = 0;
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irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqrid,
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RF_SHAREABLE | RF_ACTIVE);
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if (irqres == NULL ||
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bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE,
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NULL, adv_intr, adv, &ih) != 0) {
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if (irqres != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres);
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adv_free(adv);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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if (adv_attach(adv) != 0) {
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bus_teardown_intr(dev, irqres, ih);
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bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres);
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adv_free(adv);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
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return ENXIO;
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}
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return 0;
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}
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static device_method_t adv_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, adv_pci_probe),
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DEVMETHOD(device_attach, adv_pci_attach),
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{ 0, 0 }
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};
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static driver_t adv_pci_driver = {
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"adv", adv_pci_methods, sizeof(struct adv_softc)
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};
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static devclass_t adv_pci_devclass;
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DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);
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MODULE_DEPEND(adv, pci, 1, 1, 1);
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