2e21a3ef7e
is derived from the phrase 'MegaRAID Firmware Interface' used by LSI. This driver provides a block interface to logical disks on the card and a minimal management device. It is MPSAFE, INTR_FAST, and 64-bit capable. Thanks to Dell for providing hardware to test with and IronPort for sponsoring the work. Sponsored by: Dell, Ironport MFC After: 3 days
560 lines
15 KiB
C
560 lines
15 KiB
C
/*-
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* Copyright (c) 2006 IronPort Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MFIREG_H
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#define _MFIREG_H
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* MegaRAID SAS MFI firmware definitions
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*
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* Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely
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* new firmware interface from the old AMI MegaRAID one, and there is no
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* reason why this interface should be limited to just SAS. In any case, LSI
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* seems to also call this interface 'MFI', so that will be used here.
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*/
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/*
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* Start with the register set. All registers are 32 bits wide.
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* The usual Intel IOP style setup.
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*/
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#define MFI_IMSG0 0x10 /* Inbound message 0 */
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#define MFI_IMSG1 0x14 /* Inbound message 1 */
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#define MFI_OMSG0 0x18 /* Outbound message 0 */
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#define MFI_OMSG1 0x1c /* Outbound message 1 */
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#define MFI_IDB 0x20 /* Inbound doorbell */
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#define MFI_ISTS 0x24 /* Inbound interrupt status */
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#define MFI_IMSK 0x28 /* Inbound interrupt mask */
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#define MFI_ODB 0x2c /* Outbound doorbell */
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#define MFI_OSTS 0x30 /* Outbound interrupt status */
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#define MFI_OMSK 0x34 /* Outbound interrupt mask */
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#define MFI_IQP 0x40 /* Inbound queue port */
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#define MFI_OQP 0x44 /* Outbound queue port */
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/* Bits for MFI_OSTS */
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#define MFI_OSTS_INTR_VALID 0x00000002
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/*
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* Firmware state values. Found in OMSG0 during initialization.
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*/
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#define MFI_FWSTATE_MASK 0xf0000000
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#define MFI_FWSTATE_UNDEFINED 0x00000000
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#define MFI_FWSTATE_BB_INIT 0x10000000
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#define MFI_FWSTATE_FW_INIT 0x40000000
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#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000
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#define MFI_FWSTATE_FW_INIT_2 0x70000000
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#define MFI_FWSTATE_DEVICE_SCAN 0x80000000
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#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000
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#define MFI_FWSTATE_READY 0xb0000000
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#define MFI_FWSTATE_OPERATIONAL 0xc0000000
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#define MFI_FWSTATE_FAULT 0xf0000000
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#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000
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#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff
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/*
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* Control bits to drive the card to ready state. These go into the IDB
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* register.
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*/
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#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */
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#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */
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#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */
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#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
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/* MFI Commands */
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typedef enum {
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MFI_CMD_INIT = 0x00,
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MFI_CMD_LD_READ,
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MFI_CMD_LD_WRITE,
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MFI_CMD_LD_SCSI_IO,
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MFI_CMD_PD_SCSI_IO,
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MFI_CMD_DCMD,
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MFI_CMD_ABORT,
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MFI_CMD_SMP,
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MFI_CMD_STP
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} mfi_cmd_t;
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/* Direct commands */
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typedef enum {
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MFI_DCMD_CTRL_GETINFO = 0x01010000,
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MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000,
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MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
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MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
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MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
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MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
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MFI_DCMD_LD_GET_PROP = 0x03030000,
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MFI_DCMD_CLUSTER = 0x08000000,
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MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
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MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
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} mfi_dcmd_t;
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/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
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#define MFI_FLUSHCACHE_CTRL 0x01
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#define MFI_FLUSHCACHE_DISK 0x02
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/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
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#define MFI_SHUTDOWN_SPINDOWN 0x01
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/*
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* MFI Frmae flags
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*/
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#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
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#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
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#define MFI_FRAME_SGL32 0x0000
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#define MFI_FRAME_SGL64 0x0002
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#define MFI_FRAME_SENSE32 0x0000
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#define MFI_FRAME_SENSE64 0x0004
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#define MFI_FRAME_DIR_NONE 0x0000
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#define MFI_FRAME_DIR_WRITE 0x0008
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#define MFI_FRAME_DIR_READ 0x0010
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#define MFI_FRAME_DIR_BOTH 0x0018
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/* MFI Status codes */
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typedef enum {
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MFI_STAT_OK = 0x00,
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MFI_STAT_INVALID_CMD,
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MFI_STAT_INVALID_DCMD,
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MFI_STAT_INVALID_PARAMETER,
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MFI_STAT_INVALID_SEQUENCE_NUMBER,
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MFI_STAT_ABORT_NOT_POSSIBLE,
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MFI_STAT_APP_HOST_CODE_NOT_FOUND,
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MFI_STAT_APP_IN_USE,
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MFI_STAT_APP_NOT_INITIALIZED,
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MFI_STAT_ARRAY_INDEX_INVALID,
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MFI_STAT_ARRAY_ROW_NOT_EMPTY,
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MFI_STAT_CONFIG_RESOURCE_CONFLICT,
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MFI_STAT_DEVICE_NOT_FOUND,
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MFI_STAT_DRIVE_TOO_SMALL,
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MFI_STAT_FLASH_ALLOC_FAIL,
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MFI_STAT_FLASH_BUSY,
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MFI_STAT_FLASH_ERROR = 0x10,
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MFI_STAT_FLASH_IMAGE_BAD,
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MFI_STAT_FLASH_IMAGE_INCOMPLETE,
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MFI_STAT_FLASH_NOT_OPEN,
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MFI_STAT_FLASH_NOT_STARTED,
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MFI_STAT_FLUSH_FAILED,
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MFI_STAT_HOST_CODE_NOT_FOUNT,
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MFI_STAT_LD_CC_IN_PROGRESS,
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MFI_STAT_LD_INIT_IN_PROGRESS,
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MFI_STAT_LD_LBA_OUT_OF_RANGE,
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MFI_STAT_LD_MAX_CONFIGURED,
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MFI_STAT_LD_NOT_OPTIMAL,
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MFI_STAT_LD_RBLD_IN_PROGRESS,
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MFI_STAT_LD_RECON_IN_PROGRESS,
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MFI_STAT_LD_WRONG_RAID_LEVEL,
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MFI_STAT_MAX_SPARES_EXCEEDED,
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MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
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MFI_STAT_MFC_HW_ERROR,
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MFI_STAT_NO_HW_PRESENT,
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MFI_STAT_NOT_FOUND,
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MFI_STAT_NOT_IN_ENCL,
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MFI_STAT_PD_CLEAR_IN_PROGRESS,
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MFI_STAT_PD_TYPE_WRONG,
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MFI_STAT_PR_DISABLED,
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MFI_STAT_ROW_INDEX_INVALID,
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MFI_STAT_SAS_CONFIG_INVALID_ACTION,
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MFI_STAT_SAS_CONFIG_INVALID_DATA,
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MFI_STAT_SAS_CONFIG_INVALID_PAGE,
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MFI_STAT_SAS_CONFIG_INVALID_TYPE,
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MFI_STAT_SCSI_DONE_WITH_ERROR,
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MFI_STAT_SCSI_IO_FAILED,
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MFI_STAT_SCSI_RESERVATION_CONFLICT,
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MFI_STAT_SHUTDOWN_FAILED = 0x30,
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MFI_STAT_TIME_NOT_SET,
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MFI_STAT_WRONG_STATE,
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MFI_STAT_LD_OFFLINE,
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MFI_STAT_PEER_NOTIFICATION_REJECTED,
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MFI_STAT_PEER_NOTIFICATION_FAILED,
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MFI_STAT_RESERVATION_IN_PROGRESS,
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MFI_STAT_I2C_ERRORS_DETECTED,
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MFI_STAT_PCI_ERRORS_DETECTED,
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MFI_STAT_INVALID_STATUS = 0xFF
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} mfi_status_t;
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typedef enum {
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MFI_EVT_CLASS_DEBUG = -2,
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MFI_EVT_CLASS_PROGRESS = -1,
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MFI_EVT_CLASS_INFO = 0,
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MFI_EVT_CLASS_WARNING = 1,
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MFI_EVT_CLASS_CRITICAL = 2,
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MFI_EVT_CLASS_FATAL = 3,
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MFI_EVT_CLASS_DEAD = 4
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} mfi_evt_class_t;
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typedef enum {
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MFI_EVT_LOCALE_LD = 0x0001,
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MFI_EVT_LOCALE_PD = 0x0002,
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MFI_EVT_LOCALE_ENCL = 0x0004,
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MFI_EVT_LOCALE_BBU = 0x0008,
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MFI_EVT_LOCALE_SAS = 0x0010,
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MFI_EVT_LOCALE_CTRL = 0x0020,
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MFI_EVT_LOCALE_CONFIG = 0x0040,
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MFI_EVT_LOCALE_CLUSTER = 0x0080,
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MFI_EVT_LOCALE_ALL = 0xffff
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} mfi_evt_locale_t;
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typedef enum {
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MR_EVT_ARGS_NONE = 0x00,
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MR_EVT_ARGS_CDB_SENSE,
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MR_EVT_ARGS_LD,
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MR_EVT_ARGS_LD_COUNT,
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MR_EVT_ARGS_LD_LBA,
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MR_EVT_ARGS_LD_OWNER,
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MR_EVT_ARGS_LD_LBA_PD_LBA,
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MR_EVT_ARGS_LD_PROG,
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MR_EVT_ARGS_LD_STATE,
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MR_EVT_ARGS_LD_STRIP,
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MR_EVT_ARGS_PD,
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MR_EVT_ARGS_PD_ERR,
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MR_EVT_ARGS_PD_LBA,
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MR_EVT_ARGS_PD_LBA_LD,
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MR_EVT_ARGS_PD_PROG,
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MR_EVT_ARGS_PD_STATE,
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MR_EVT_ARGS_PCI,
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MR_EVT_ARGS_RATE,
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MR_EVT_ARGS_STR,
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MR_EVT_ARGS_TIME,
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MR_EVT_ARGS_ECC
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} mfi_evt_args;
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/*
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* Other propertities and definitions
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*/
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#define MFI_MAX_PD_CHANNELS 2
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#define MFI_MAX_LD_CHANNELS 2
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#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
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#define MFI_MAX_CHANNEL_DEVS 128
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#define MFI_DEFAULT_ID -1
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#define MFI_MAX_LUN 8
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#define MFI_MAX_LD 64
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#define MFI_FRAME_SIZE 64
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#define MFI_MBOX_SIZE 12
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#define MFI_POLL_TIMEOUT_SECS 10
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/* Allow for speedier math calculations */
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#define MFI_SECTOR_LEN 512
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/* Scatter Gather elements */
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struct mfi_sg32 {
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uint32_t addr;
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uint32_t len;
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} __packed;
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struct mfi_sg64 {
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uint64_t addr;
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uint32_t len;
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} __packed;
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union mfi_sgl {
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struct mfi_sg32 sg32[1];
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struct mfi_sg64 sg64[1];
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} __packed;
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/* Message frames. All messages have a common header */
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struct mfi_frame_header {
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uint8_t cmd;
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uint8_t sense_len;
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uint8_t cmd_status;
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uint8_t scsi_status;
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uint8_t target_id;
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uint8_t lun_id;
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uint8_t cdb_len;
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uint8_t sg_count;
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uint32_t context;
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uint32_t pad0;
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uint16_t flags;
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uint16_t timeout;
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uint32_t data_len;
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} __packed;
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struct mfi_init_frame {
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struct mfi_frame_header header;
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uint32_t qinfo_new_addr_lo;
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uint32_t qinfo_new_addr_hi;
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uint32_t qinfo_old_addr_lo;
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uint32_t qinfo_old_addr_hi;
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uint32_t reserved[6];
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} __packed;
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#define MFI_IO_FRAME_SIZE 40
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struct mfi_io_frame {
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struct mfi_frame_header header;
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uint32_t sense_addr_lo;
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uint32_t sense_addr_hi;
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uint32_t lba_lo;
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uint32_t lba_hi;
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union mfi_sgl sgl;
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} __packed;
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#define MFI_PASS_FRAME_SIZE 48
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struct mfi_pass_frame {
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struct mfi_frame_header header;
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uint32_t sense_addr_lo;
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uint32_t sense_addr_hi;
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uint8_t cdb[16];
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union mfi_sgl sgl;
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} __packed;
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#define MFI_DCMD_FRAME_SIZE 40
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struct mfi_dcmd_frame {
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struct mfi_frame_header header;
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uint32_t opcode;
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uint8_t mbox[MFI_MBOX_SIZE];
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union mfi_sgl sgl;
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} __packed;
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struct mfi_abort_frame {
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struct mfi_frame_header header;
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uint32_t abort_context;
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uint32_t pad;
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uint32_t abort_mfi_addr_lo;
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uint32_t abort_mfi_addr_hi;
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uint32_t reserved[6];
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} __packed;
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struct mfi_smp_frame {
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struct mfi_frame_header header;
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uint64_t sas_addr;
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union {
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struct mfi_sg32 sg32[2];
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struct mfi_sg64 sg64[2];
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} sgl;
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} __packed;
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struct mfi_stp_frame {
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struct mfi_frame_header header;
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uint16_t fis[10];
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uint32_t stp_flags;
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union {
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struct mfi_sg32 sg32[2];
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struct mfi_sg64 sg64[2];
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} sgl;
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} __packed;
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union mfi_frame {
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struct mfi_frame_header header;
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struct mfi_init_frame init;
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struct mfi_io_frame io;
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struct mfi_pass_frame pass;
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struct mfi_dcmd_frame dcmd;
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struct mfi_abort_frame abort;
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struct mfi_smp_frame smp;
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struct mfi_stp_frame stp;
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uint8_t bytes[MFI_FRAME_SIZE];
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};
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#define MFI_SENSE_LEN 128
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struct mfi_sense {
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uint8_t data[MFI_SENSE_LEN];
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};
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/* The queue init structure that is passed with the init message */
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struct mfi_init_qinfo {
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uint32_t flags;
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uint32_t rq_entries;
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uint32_t rq_addr_lo;
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uint32_t rq_addr_hi;
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uint32_t pi_addr_lo;
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uint32_t pi_addr_hi;
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uint32_t ci_addr_lo;
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uint32_t ci_addr_hi;
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} __packed;
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/* SAS (?) controller properties, part of mfi_ctrl_info */
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struct mfi_ctrl_props {
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uint16_t seq_num;
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uint16_t pred_fail_poll_interval;
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uint16_t intr_throttle_cnt;
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uint16_t intr_throttle_timeout;
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uint8_t rebuild_rate;
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uint8_t patrol_read_rate;
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uint8_t bgi_rate;
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uint8_t cc_rate;
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uint8_t recon_rate;
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uint8_t cache_flush_interval;
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uint8_t spinup_drv_cnt;
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uint8_t spinup_delay;
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uint8_t cluster_enable;
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uint8_t coercion_mode;
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uint8_t alarm_enable;
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uint8_t disable_auto_rebuild;
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uint8_t disable_battery_warn;
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uint8_t ecc_bucket_size;
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uint16_t ecc_bucket_leak_rate;
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uint8_t restore_hotspare_on_insertion;
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uint8_t expose_encl_devices;
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uint8_t reserved[38];
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} __packed;
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/* PCI information about the card. */
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struct mfi_info_pci {
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uint16_t vendor;
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uint16_t device;
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uint16_t subvendor;
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uint16_t subdevice;
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uint8_t reserved[24];
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} __packed;
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/* Host (front end) interface information */
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struct mfi_info_host {
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uint8_t type;
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#define MFI_INFO_HOST_PCIX 0x01
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#define MFI_INFO_HOST_PCIE 0x02
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#define MFI_INFO_HOST_ISCSI 0x04
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#define MFI_INFO_HOST_SAS3G 0x08
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uint8_t reserved[6];
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uint8_t port_count;
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uint64_t port_addr[8];
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} __packed;
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/* Device (back end) interface information */
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struct mfi_info_device {
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uint8_t type;
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#define MFI_INFO_DEV_SPI 0x01
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#define MFI_INFO_DEV_SAS3G 0x02
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#define MFI_INFO_DEV_SATA1 0x04
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#define MFI_INFO_DEV_SATA3G 0x08
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uint8_t reserved[6];
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uint8_t port_count;
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uint64_t port_addr[8];
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} __packed;
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/* Firmware component information */
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struct mfi_info_component {
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char name[8];
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char version[32];
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char build_date[16];
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char build_time[16];
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} __packed;
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/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
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struct mfi_ctrl_info {
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struct mfi_info_pci pci;
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struct mfi_info_host host;
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struct mfi_info_device device;
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/* Firmware components that are present and active. */
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uint32_t image_check_word;
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uint32_t image_component_count;
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struct mfi_info_component image_component[8];
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/* Firmware components that have been flashed but are inactive */
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uint32_t pending_image_component_count;
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struct mfi_info_component pending_image_component[8];
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uint8_t max_arms;
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uint8_t max_spans;
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uint8_t max_arrays;
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uint8_t max_lds;
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char product_name[80];
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char serial_number[32];
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uint32_t hw_present;
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#define MFI_INFO_HW_BBU 0x01
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#define MFI_INFO_HW_ALARM 0x02
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#define MFI_INFO_HW_NVRAM 0x04
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#define MFI_INFO_HW_UART 0x08
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uint32_t current_fw_time;
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uint16_t max_cmds;
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uint16_t max_sg_elements;
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uint32_t max_request_size;
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uint16_t lds_present;
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uint16_t lds_degraded;
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uint16_t lds_offline;
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uint16_t pd_present;
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uint16_t pd_disks_present;
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uint16_t pd_disks_pred_failure;
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uint16_t pd_disks_failed;
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uint16_t nvram_size;
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uint16_t memory_size;
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uint16_t flash_size;
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uint16_t ram_correctable_errors;
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uint16_t ram_uncorrectable_errors;
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uint8_t cluster_allowed;
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uint8_t cluster_active;
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uint16_t max_strips_per_io;
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uint32_t raid_levels;
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#define MFI_INFO_RAID_0 0x01
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#define MFI_INFO_RAID_1 0x02
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#define MFI_INFO_RAID_5 0x04
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#define MFI_INFO_RAID_1E 0x08
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#define MFI_INFO_RAID_6 0x10
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uint32_t adapter_ops;
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#define MFI_INFO_AOPS_RBLD_RATE 0x0001
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#define MFI_INFO_AOPS_CC_RATE 0x0002
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#define MFI_INFO_AOPS_BGI_RATE 0x0004
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#define MFI_INFO_AOPS_RECON_RATE 0x0008
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#define MFI_INFO_AOPS_PATROL_RATE 0x0010
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#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
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#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
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#define MFI_INFO_AOPS_BBU 0x0080
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#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
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#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
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#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
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#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
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#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
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#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
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#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
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uint32_t ld_ops;
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#define MFI_INFO_LDOPS_READ_POLICY 0x01
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#define MFI_INFO_LDOPS_WRITE_POLICY 0x02
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#define MFI_INFO_LDOPS_IO_POLICY 0x04
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#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
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#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
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struct {
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uint8_t min;
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uint8_t max;
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uint8_t reserved[2];
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} __packed stripe_sz_ops;
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uint32_t pd_ops;
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#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
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#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
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#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
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uint32_t pd_mix_support;
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#define MFI_INFO_PDMIX_SAS 0x01
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#define MFI_INFO_PDMIX_SATA 0x02
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#define MFI_INFO_PDMIX_ENCL 0x04
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#define MFI_INFO_PDMIX_LD 0x08
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#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
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uint8_t ecc_bucket_count;
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uint8_t reserved2[11];
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struct mfi_ctrl_props properties;
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char package_version[0x60];
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uint8_t pad[0x800 - 0x6a0];
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} __packed;
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#endif /* _MFIREG_H */
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