644 lines
16 KiB
C
644 lines
16 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Routines to handle clock hardware.
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*/
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#include "opt_apic.h"
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#include "opt_clock.h"
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#include "opt_kdtrace.h"
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#include "opt_isa.h"
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#include "opt_mca.h"
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#include "opt_xbox.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/kdb.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/timetc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/sched.h>
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#include <sys/sysctl.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#ifdef DEV_APIC
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#include <machine/apicvar.h>
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#endif
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#include <machine/ppireg.h>
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#include <machine/timerreg.h>
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#include <isa/rtc.h>
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#ifdef DEV_ISA
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#endif
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#ifdef DEV_MCA
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#include <i386/bios/mca_machdep.h>
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#endif
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#ifdef KDTRACE_HOOKS
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#include <sys/dtrace_bsd.h>
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#endif
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#define TIMER_DIV(x) ((i8254_freq + (x) / 2) / (x))
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int clkintr_pending;
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static int pscnt = 1;
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static int psdiv = 1;
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int statclock_disable;
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#ifndef TIMER_FREQ
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#define TIMER_FREQ 1193182
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#endif
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u_int i8254_freq = TIMER_FREQ;
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TUNABLE_INT("hw.i8254.freq", &i8254_freq);
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int i8254_max_count;
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static int i8254_real_max_count;
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struct mtx clock_lock;
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static struct intsrc *i8254_intsrc;
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static u_int32_t i8254_lastcount;
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static u_int32_t i8254_offset;
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static int (*i8254_pending)(struct intsrc *);
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static int i8254_ticked;
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static int using_lapic_timer;
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/* Values for timerX_state: */
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#define RELEASED 0
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#define RELEASE_PENDING 1
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#define ACQUIRED 2
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#define ACQUIRE_PENDING 3
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static u_char timer2_state;
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static unsigned i8254_get_timecount(struct timecounter *tc);
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static unsigned i8254_simple_get_timecount(struct timecounter *tc);
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static void set_i8254_freq(u_int freq, int intr_freq);
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static struct timecounter i8254_timecounter = {
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i8254_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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0, /* frequency */
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"i8254", /* name */
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0 /* quality */
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};
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static int
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clkintr(struct trapframe *frame)
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{
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if (timecounter->tc_get_timecount == i8254_get_timecount) {
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mtx_lock_spin(&clock_lock);
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if (i8254_ticked)
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i8254_ticked = 0;
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else {
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i8254_offset += i8254_max_count;
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i8254_lastcount = 0;
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}
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clkintr_pending = 0;
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mtx_unlock_spin(&clock_lock);
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}
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KASSERT(!using_lapic_timer, ("clk interrupt enabled with lapic timer"));
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#ifdef KDTRACE_HOOKS
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/*
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* If the DTrace hooks are configured and a callback function
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* has been registered, then call it to process the high speed
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* timers.
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*/
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int cpu = PCPU_GET(cpuid);
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if (lapic_cyclic_clock_func[cpu] != NULL)
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(*lapic_cyclic_clock_func[cpu])(frame);
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#endif
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hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
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#ifdef DEV_MCA
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/* Reset clock interrupt by asserting bit 7 of port 0x61 */
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if (MCA_system)
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outb(0x61, inb(0x61) | 0x80);
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#endif
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return (FILTER_HANDLED);
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}
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int
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timer_spkr_acquire(void)
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{
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int mode;
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mode = TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT;
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if (timer2_state != RELEASED)
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return (-1);
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timer2_state = ACQUIRED;
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/*
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* This access to the timer registers is as atomic as possible
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* because it is a single instruction. We could do better if we
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* knew the rate. Use of splclock() limits glitches to 10-100us,
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* and this is probably good enough for timer2, so we aren't as
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* careful with it as with timer0.
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*/
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outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
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ppi_spkr_on(); /* enable counter2 output to speaker */
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return (0);
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}
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int
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timer_spkr_release(void)
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{
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if (timer2_state != ACQUIRED)
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return (-1);
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timer2_state = RELEASED;
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outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
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ppi_spkr_off(); /* disable counter2 output to speaker */
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return (0);
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}
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void
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timer_spkr_setfreq(int freq)
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{
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freq = i8254_freq / freq;
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mtx_lock_spin(&clock_lock);
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outb(TIMER_CNTR2, freq & 0xff);
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outb(TIMER_CNTR2, freq >> 8);
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mtx_unlock_spin(&clock_lock);
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}
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/*
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* This routine receives statistical clock interrupts from the RTC.
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* As explained above, these occur at 128 interrupts per second.
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* When profiling, we receive interrupts at a rate of 1024 Hz.
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*
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* This does not actually add as much overhead as it sounds, because
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* when the statistical clock is active, the hardclock driver no longer
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* needs to keep (inaccurate) statistics on its own. This decouples
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* statistics gathering from scheduling interrupts.
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*
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* The RTC chip requires that we read status register C (RTC_INTR)
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* to acknowledge an interrupt, before it will generate the next one.
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* Under high interrupt load, rtcintr() can be indefinitely delayed and
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* the clock can tick immediately after the read from RTC_INTR. In this
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* case, the mc146818A interrupt signal will not drop for long enough
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* to register with the 8259 PIC. If an interrupt is missed, the stat
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* clock will halt, considerably degrading system performance. This is
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* why we use 'while' rather than a more straightforward 'if' below.
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* Stat clock ticks can still be lost, causing minor loss of accuracy
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* in the statistics, but the stat clock will no longer stop.
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*/
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static int
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rtcintr(struct trapframe *frame)
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{
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int flag = 0;
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while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
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flag = 1;
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if (profprocs != 0) {
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if (--pscnt == 0)
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pscnt = psdiv;
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profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
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}
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if (pscnt == psdiv)
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statclock(TRAPF_USERMODE(frame));
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}
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return(flag ? FILTER_HANDLED : FILTER_STRAY);
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}
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static int
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getit(void)
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{
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int high, low;
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mtx_lock_spin(&clock_lock);
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/* Select timer0 and latch counter value. */
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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mtx_unlock_spin(&clock_lock);
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return ((high << 8) | low);
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}
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/*
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* Wait "n" microseconds.
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* Relies on timer 1 counting down from (i8254_freq / hz)
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* Note: timer had better have been programmed before this is first used!
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*/
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void
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DELAY(int n)
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{
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int delta, prev_tick, tick, ticks_left;
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#ifdef DELAYDEBUG
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int getit_calls = 1;
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int n1;
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static int state = 0;
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#endif
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if (tsc_freq != 0 && !tsc_is_broken) {
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uint64_t start, end, now;
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sched_pin();
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start = rdtsc();
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end = start + (tsc_freq * n) / 1000000;
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do {
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cpu_spinwait();
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now = rdtsc();
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} while (now < end || (now > start && end < start));
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sched_unpin();
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return;
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}
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#ifdef DELAYDEBUG
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if (state == 0) {
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state = 1;
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for (n1 = 1; n1 <= 10000000; n1 *= 10)
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DELAY(n1);
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state = 2;
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}
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if (state == 1)
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printf("DELAY(%d)...", n);
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#endif
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/*
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* Read the counter first, so that the rest of the setup overhead is
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* counted. Guess the initial overhead is 20 usec (on most systems it
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* takes about 1.5 usec for each of the i/o's in getit(). The loop
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* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
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* multiplications and divisions to scale the count take a while).
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*
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* However, if ddb is active then use a fake counter since reading
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* the i8254 counter involves acquiring a lock. ddb must not do
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* locking for many reasons, but it calls here for at least atkbd
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* input.
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*/
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#ifdef KDB
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if (kdb_active)
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prev_tick = 1;
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else
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#endif
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prev_tick = getit();
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n -= 0; /* XXX actually guess no initial overhead */
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/*
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* Calculate (n * (i8254_freq / 1e6)) without using floating point
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* and without any avoidable overflows.
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*/
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if (n <= 0)
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ticks_left = 0;
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else if (n < 256)
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/*
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* Use fixed point to avoid a slow division by 1000000.
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* 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
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* 2^15 is the first power of 2 that gives exact results
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* for n between 0 and 256.
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*/
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ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
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else
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/*
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* Don't bother using fixed point, although gcc-2.7.2
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* generates particularly poor code for the long long
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* division, since even the slow way will complete long
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* before the delay is up (unless we're interrupted).
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*/
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ticks_left = ((u_int)n * (long long)i8254_freq + 999999)
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/ 1000000;
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while (ticks_left > 0) {
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#ifdef KDB
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if (kdb_active) {
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inb(0x84);
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tick = prev_tick - 1;
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if (tick <= 0)
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tick = i8254_max_count;
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} else
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#endif
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tick = getit();
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#ifdef DELAYDEBUG
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++getit_calls;
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#endif
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delta = prev_tick - tick;
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prev_tick = tick;
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if (delta < 0) {
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delta += i8254_max_count;
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/*
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* Guard against i8254_max_count being wrong.
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* This shouldn't happen in normal operation,
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* but it may happen if set_i8254_freq() is
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* traced.
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*/
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if (delta < 0)
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delta = 0;
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}
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ticks_left -= delta;
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}
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#ifdef DELAYDEBUG
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if (state == 1)
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printf(" %d calls to getit() at %d usec each\n",
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getit_calls, (n + 5) / getit_calls);
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#endif
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}
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static void
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set_i8254_freq(u_int freq, int intr_freq)
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{
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int new_i8254_real_max_count;
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i8254_timecounter.tc_frequency = freq;
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mtx_lock_spin(&clock_lock);
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i8254_freq = freq;
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if (using_lapic_timer)
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new_i8254_real_max_count = 0x10000;
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else
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new_i8254_real_max_count = TIMER_DIV(intr_freq);
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if (new_i8254_real_max_count != i8254_real_max_count) {
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i8254_real_max_count = new_i8254_real_max_count;
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if (i8254_real_max_count == 0x10000)
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i8254_max_count = 0xffff;
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else
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i8254_max_count = i8254_real_max_count;
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, i8254_real_max_count & 0xff);
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outb(TIMER_CNTR0, i8254_real_max_count >> 8);
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}
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mtx_unlock_spin(&clock_lock);
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}
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static void
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i8254_restore(void)
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{
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mtx_lock_spin(&clock_lock);
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, i8254_real_max_count & 0xff);
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outb(TIMER_CNTR0, i8254_real_max_count >> 8);
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mtx_unlock_spin(&clock_lock);
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}
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/*
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* Restore all the timers non-atomically (XXX: should be atomically).
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*
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* This function is called from pmtimer_resume() to restore all the timers.
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* This should not be necessary, but there are broken laptops that do not
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* restore all the timers on resume.
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*/
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void
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timer_restore(void)
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{
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i8254_restore(); /* restore i8254_freq and hz */
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atrtc_restore(); /* reenable RTC interrupts */
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}
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/* This is separate from startrtclock() so that it can be called early. */
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void
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i8254_init(void)
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{
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mtx_init(&clock_lock, "clk", NULL, MTX_SPIN | MTX_NOPROFILE);
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set_i8254_freq(i8254_freq, hz);
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}
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void
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startrtclock()
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{
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atrtc_start();
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set_i8254_freq(i8254_freq, hz);
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tc_init(&i8254_timecounter);
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init_TSC();
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}
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/*
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* Start both clocks running.
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*/
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void
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cpu_initclocks()
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{
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int diag;
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#ifdef DEV_APIC
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using_lapic_timer = lapic_setup_clock();
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#endif
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/*
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* If we aren't using the local APIC timer to drive the kernel
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* clocks, setup the interrupt handler for the 8254 timer 0 so
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* that it can drive hardclock(). Otherwise, change the 8254
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* timecounter to user a simpler algorithm.
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*/
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if (!using_lapic_timer) {
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intr_add_handler("clk", 0, (driver_filter_t *)clkintr, NULL,
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NULL, INTR_TYPE_CLK, NULL);
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i8254_intsrc = intr_lookup_source(0);
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if (i8254_intsrc != NULL)
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i8254_pending =
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i8254_intsrc->is_pic->pic_source_pending;
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} else {
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i8254_timecounter.tc_get_timecount =
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i8254_simple_get_timecount;
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i8254_timecounter.tc_counter_mask = 0xffff;
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set_i8254_freq(i8254_freq, hz);
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}
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/* Initialize RTC. */
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atrtc_start();
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/*
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* If the separate statistics clock hasn't been explicility disabled
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* and we aren't already using the local APIC timer to drive the
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* kernel clocks, then setup the RTC to periodically interrupt to
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* drive statclock() and profclock().
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*/
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if (!statclock_disable && !using_lapic_timer) {
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diag = rtcin(RTC_DIAG);
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if (diag != 0)
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printf("RTC BIOS diagnostic error %b\n",
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diag, RTCDG_BITS);
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/* Setting stathz to nonzero early helps avoid races. */
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stathz = RTC_NOPROFRATE;
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profhz = RTC_PROFRATE;
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/* Enable periodic interrupts from the RTC. */
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intr_add_handler("rtc", 8,
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(driver_filter_t *)rtcintr, NULL, NULL,
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INTR_TYPE_CLK, NULL);
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atrtc_enable_intr();
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}
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init_TSC_tc();
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}
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void
|
|
cpu_startprofclock(void)
|
|
{
|
|
|
|
if (using_lapic_timer)
|
|
return;
|
|
atrtc_rate(RTCSA_PROF);
|
|
psdiv = pscnt = psratio;
|
|
}
|
|
|
|
void
|
|
cpu_stopprofclock(void)
|
|
{
|
|
|
|
if (using_lapic_timer)
|
|
return;
|
|
atrtc_rate(RTCSA_NOPROF);
|
|
psdiv = pscnt = 1;
|
|
}
|
|
|
|
static int
|
|
sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
int error;
|
|
u_int freq;
|
|
|
|
/*
|
|
* Use `i8254' instead of `timer' in external names because `timer'
|
|
* is is too generic. Should use it everywhere.
|
|
*/
|
|
freq = i8254_freq;
|
|
error = sysctl_handle_int(oidp, &freq, 0, req);
|
|
if (error == 0 && req->newptr != NULL)
|
|
set_i8254_freq(freq, hz);
|
|
return (error);
|
|
}
|
|
|
|
SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
|
|
0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
|
|
|
|
static unsigned
|
|
i8254_simple_get_timecount(struct timecounter *tc)
|
|
{
|
|
|
|
return (i8254_max_count - getit());
|
|
}
|
|
|
|
static unsigned
|
|
i8254_get_timecount(struct timecounter *tc)
|
|
{
|
|
u_int count;
|
|
u_int high, low;
|
|
u_int eflags;
|
|
|
|
eflags = read_eflags();
|
|
mtx_lock_spin(&clock_lock);
|
|
|
|
/* Select timer0 and latch counter value. */
|
|
outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
|
|
|
|
low = inb(TIMER_CNTR0);
|
|
high = inb(TIMER_CNTR0);
|
|
count = i8254_max_count - ((high << 8) | low);
|
|
if (count < i8254_lastcount ||
|
|
(!i8254_ticked && (clkintr_pending ||
|
|
((count < 20 || (!(eflags & PSL_I) &&
|
|
count < i8254_max_count / 2u)) &&
|
|
i8254_pending != NULL && i8254_pending(i8254_intsrc))))) {
|
|
i8254_ticked = 1;
|
|
i8254_offset += i8254_max_count;
|
|
}
|
|
i8254_lastcount = count;
|
|
count += i8254_offset;
|
|
mtx_unlock_spin(&clock_lock);
|
|
return (count);
|
|
}
|
|
|
|
#ifdef DEV_ISA
|
|
/*
|
|
* Attach to the ISA PnP descriptors for the timer
|
|
*/
|
|
static struct isa_pnp_id attimer_ids[] = {
|
|
{ 0x0001d041 /* PNP0100 */, "AT timer" },
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
attimer_probe(device_t dev)
|
|
{
|
|
int result;
|
|
|
|
result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids);
|
|
if (result <= 0)
|
|
device_quiet(dev);
|
|
return(result);
|
|
}
|
|
|
|
static int
|
|
attimer_attach(device_t dev)
|
|
{
|
|
return(0);
|
|
}
|
|
|
|
static device_method_t attimer_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, attimer_probe),
|
|
DEVMETHOD(device_attach, attimer_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t attimer_driver = {
|
|
"attimer",
|
|
attimer_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t attimer_devclass;
|
|
|
|
DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
|
|
DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
|
|
|
|
#endif /* DEV_ISA */
|