30924ed343
shifting. Also correct the original code as Garrett noticed it in mail. Leave the mishandled code in to use it later if future versions of gcc are correct. The code was part of the calibrate_cyclecounter routine to get the speed of the pentium chip.
607 lines
16 KiB
C
607 lines
16 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.29 1994/12/30 12:43:34 bde Exp $
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*/
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/*
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* inittodr, settodr and support routines written
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* by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
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*
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* reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
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*/
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/*
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* Primitive clock interrupt routines.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <machine/clock.h>
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#include <machine/frame.h>
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#include <i386/isa/icu.h>
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#include <i386/isa/isa.h>
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#include <i386/isa/rtc.h>
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#include <i386/isa/timerreg.h>
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/*
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* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
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* can use a simple formula for leap years.
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*/
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#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
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#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
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/* X-tals being what they are, it's nice to be able to fudge this one... */
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#ifndef TIMER_FREQ
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#define TIMER_FREQ 1193182 /* XXX - should be in isa.h */
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#endif
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#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
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/*
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* Time in timer cycles that it takes for microtime() to disable interrupts
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* and latch the count. microtime() currently uses "cli; outb ..." so it
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* normally takes less than 2 timer cycles. Add a few for cache misses.
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* Add a few more to allow for latency in bogus calls to microtime() with
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* interrupts already disabled.
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*/
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#define TIMER0_LATCH_COUNT 20
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/*
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* Minimum maximum count that we are willing to program into timer0.
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* Must be large enough to guarantee that the timer interrupt handler
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* returns before the next timer interrupt. Must be larger than
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* TIMER0_LATCH_COUNT so that we don't have to worry about underflow in
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* the calculation of timer0_overflow_threshold.
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*/
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#define TIMER0_MIN_MAX_COUNT TIMER_DIV(20000)
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int adjkerntz = 0; /* offset from CMOS clock */
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int disable_rtc_set = 0; /* disable resettodr() if != 0 */
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#ifdef I586_CPU
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int pentium_mhz;
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#endif
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u_int stat_imask = SWI_CLOCK_MASK;
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int timer0_max_count;
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u_int timer0_overflow_threshold;
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u_int timer0_prescaler_count;
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static int beeping = 0;
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static u_int clk_imask = HWI_MASK | SWI_MASK;
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static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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static u_int hardclock_max_count;
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/*
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* XXX new_function and timer_func should not handle clockframes, but
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* timer_func currently needs to hold hardclock to handle the
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* timer0_state == 0 case. We should use register_intr()/unregister_intr()
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* to switch between clkintr() and a slightly different timerintr().
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* This will require locking when acquiring and releasing timer0 - the
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* current (nonexistent) locking doesn't seem to be adequate even now.
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*/
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static void (*new_function) __P((struct clockframe *frame));
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static u_int new_rate;
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static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
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static char timer0_state = 0;
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static char timer2_state = 0;
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static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
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#if 0
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void
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clkintr(struct clockframe frame)
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{
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hardclock(&frame);
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}
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#else
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void
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clkintr(struct clockframe frame)
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{
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timer_func(&frame);
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switch (timer0_state) {
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case 0:
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break;
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case 1:
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if ((timer0_prescaler_count += timer0_max_count)
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>= hardclock_max_count) {
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hardclock(&frame);
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timer0_prescaler_count -= hardclock_max_count;
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}
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break;
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case 2:
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timer0_max_count = TIMER_DIV(new_rate);
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timer0_overflow_threshold =
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timer0_max_count - TIMER0_LATCH_COUNT;
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disable_intr();
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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enable_intr();
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timer0_prescaler_count = 0;
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timer_func = new_function;
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timer0_state = 1;
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break;
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case 3:
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if ((timer0_prescaler_count += timer0_max_count)
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>= hardclock_max_count) {
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hardclock(&frame);
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timer0_max_count = hardclock_max_count;
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timer0_overflow_threshold =
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timer0_max_count - TIMER0_LATCH_COUNT;
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disable_intr();
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outb(TIMER_MODE,
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TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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enable_intr();
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/*
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* See microtime.s for this magic.
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*/
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time.tv_usec += (27645 *
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(timer0_prescaler_count - hardclock_max_count))
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>> 15;
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if (time.tv_usec >= 1000000)
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time.tv_usec -= 1000000;
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timer0_prescaler_count = 0;
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timer_func = hardclock;;
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timer0_state = 0;
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}
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break;
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}
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}
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#endif
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int
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acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
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{
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if (timer0_state || TIMER_DIV(rate) < TIMER0_MIN_MAX_COUNT ||
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!function)
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return -1;
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new_function = function;
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new_rate = rate;
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timer0_state = 2;
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return 0;
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}
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int
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acquire_timer2(int mode)
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{
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if (timer2_state)
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return -1;
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timer2_state = 1;
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outb(TIMER_MODE, TIMER_SEL2 | (mode &0x3f));
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return 0;
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}
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int
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release_timer0()
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{
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if (!timer0_state)
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return -1;
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timer0_state = 3;
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return 0;
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}
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int
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release_timer2()
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{
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if (!timer2_state)
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return -1;
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timer2_state = 0;
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outb(TIMER_MODE, TIMER_SEL2|TIMER_SQWAVE|TIMER_16BIT);
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return 0;
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}
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/*
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* This routine receives statistical clock interrupts from the RTC.
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* As explained above, these occur at 128 interrupts per second.
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* When profiling, we receive interrupts at a rate of 1024 Hz.
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*
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* This does not actually add as much overhead as it sounds, because
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* when the statistical clock is active, the hardclock driver no longer
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* needs to keep (inaccurate) statistics on its own. This decouples
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* statistics gathering from scheduling interrupts.
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*
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* The RTC chip requires that we read status register C (RTC_INTR)
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* to acknowledge an interrupt, before it will generate the next one.
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*/
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void
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rtcintr(struct clockframe frame)
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{
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u_char stat;
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stat = rtcin(RTC_INTR);
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if(stat & RTCIR_PERIOD) {
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statclock(&frame);
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}
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}
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#ifdef DDB
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static void
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printrtc(void)
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{
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printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
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rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
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rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
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rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
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}
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#endif
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static int
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getit()
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{
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int high, low;
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disable_intr();
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/* select timer0 and latch counter value */
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outb(TIMER_MODE, TIMER_SEL0);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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enable_intr();
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return ((high << 8) | low);
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}
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#ifdef I586_CPU
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static long long cycles_per_sec = 0;
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/*
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* Figure out how fast the cyclecounter runs. This must be run with
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* clock interrupts disabled, but with the timer/counter programmed
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* and running.
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*/
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void
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calibrate_cyclecounter(void)
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{
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volatile long edx, eax, lasteax, lastedx;
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__asm __volatile(".byte 0x0f, 0x31" : "=a"(lasteax), "=d"(lastedx) : );
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DELAY(1000000);
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__asm __volatile(".byte 0x0f, 0x31" : "=a"(eax), "=d"(edx) : );
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/*
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* This assumes that you will never have a clock rate higher
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* than 4GHz, probably a good assumption.
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*/
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/* The following C code is correct, but our current gcc 2.6.3
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* seems to produce bad assembly code for it , ATS , XXXX */
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#if 0
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cycles_per_sec = ((long long)edx << 32) + eax;
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cycles_per_sec -= ((long long)lastedx << 32) + lasteax;
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pentium_mhz = ((long)cycles_per_sec + 500000) / 1000000; /* round up */
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#else
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/* produce a workaround for the code above */
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{
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union {
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long long extralong;
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long shorty[2];
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} tmp;
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tmp.shorty[0] = eax;
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tmp.shorty[1] = edx;
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cycles_per_sec = tmp.extralong;
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tmp.shorty[0] = lasteax;
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tmp.shorty[1] = lastedx;
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cycles_per_sec -= tmp.extralong;
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/* round up */
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pentium_mhz = (long) ((cycles_per_sec + 500000) / 1000000);
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}
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#endif
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}
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#endif
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/*
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* Wait "n" microseconds.
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* Relies on timer 1 counting down from (TIMER_FREQ / hz)
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* Note: timer had better have been programmed before this is first used!
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*/
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void
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DELAY(int n)
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{
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int prev_tick, tick, ticks_left, sec, usec;
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#ifdef DELAYDEBUG
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int getit_calls = 1;
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int n1;
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static int state = 0;
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if (state == 0) {
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state = 1;
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for (n1 = 1; n1 <= 10000000; n1 *= 10)
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DELAY(n1);
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state = 2;
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}
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if (state == 1)
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printf("DELAY(%d)...", n);
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#endif
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/*
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* Read the counter first, so that the rest of the setup overhead is
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* counted. Guess the initial overhead is 20 usec (on most systems it
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* takes about 1.5 usec for each of the i/o's in getit(). The loop
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* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
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* multiplications and divisions to scale the count take a while).
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*/
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prev_tick = getit(0, 0);
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n -= 20;
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/*
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* Calculate (n * (TIMER_FREQ / 1e6)) without using floating point
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* and without any avoidable overflows.
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*/
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sec = n / 1000000;
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usec = n - sec * 1000000;
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ticks_left = sec * TIMER_FREQ
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+ usec * (TIMER_FREQ / 1000000)
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+ usec * ((TIMER_FREQ % 1000000) / 1000) / 1000
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+ usec * (TIMER_FREQ % 1000) / 1000000;
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while (ticks_left > 0) {
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tick = getit(0, 0);
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#ifdef DELAYDEBUG
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++getit_calls;
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#endif
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if (tick > prev_tick)
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ticks_left -= prev_tick - (tick - timer0_max_count);
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else
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ticks_left -= prev_tick - tick;
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prev_tick = tick;
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}
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#ifdef DELAYDEBUG
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if (state == 1)
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printf(" %d calls to getit() at %d usec each\n",
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getit_calls, (n + 5) / getit_calls);
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#endif
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}
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static void
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sysbeepstop(void *chan)
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{
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outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
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release_timer2();
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beeping = 0;
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}
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int
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sysbeep(int pitch, int period)
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{
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if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
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return -1;
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disable_intr();
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outb(TIMER_CNTR2, pitch);
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outb(TIMER_CNTR2, (pitch>>8));
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enable_intr();
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if (!beeping) {
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outb(IO_PPI, inb(IO_PPI) | 3); /* enable counter2 output to speaker */
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beeping = period;
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timeout(sysbeepstop, (void *)NULL, period);
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}
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return 0;
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}
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/*
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* RTC support routines
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*/
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static int
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bcd2int(int bcd)
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{
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return(bcd/16 * 10 + bcd%16);
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}
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static int
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int2bcd(int dez)
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{
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return(dez/10 * 16 + dez%10);
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}
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static inline void
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writertc(u_char reg, u_char val)
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{
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outb(IO_RTC, reg);
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outb(IO_RTC + 1, val);
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}
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static int
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readrtc(int port)
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{
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return(bcd2int(rtcin(port)));
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}
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|
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/*
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* Initialize 8253 timer 0 early so that it can be used in DELAY().
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* XXX initialization of other timers is unintentionally left blank.
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*/
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void
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startrtclock()
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{
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timer0_max_count = hardclock_max_count = TIMER_DIV(hz);
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timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT;
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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}
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/*
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* Initialize the time of day register, based on the time base which is, e.g.
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* from a filesystem.
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*/
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void
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inittodr(time_t base)
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{
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unsigned long sec, days;
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int yd;
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int year, month;
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int y, m, s;
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|
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s = splclock();
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time.tv_sec = base;
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time.tv_usec = 0;
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splx(s);
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|
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/* Look if we have a RTC present and the time is valid */
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if (rtcin(RTC_STATUSD) != RTCSD_PWR)
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goto wrong_time;
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|
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/* wait for time update to complete */
|
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/* If RTCSA_TUP is zero, we have at least 244us before next update */
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while (rtcin(RTC_STATUSA) & RTCSA_TUP);
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days = 0;
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#ifdef USE_RTC_CENTURY
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year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
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#else
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year = readrtc(RTC_YEAR) + 1900;
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if (year < 1970)
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year += 100;
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#endif
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if (year < 1970)
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goto wrong_time;
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month = readrtc(RTC_MONTH);
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for (m = 1; m < month; m++)
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days += daysinmonth[m-1];
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if ((month > 2) && LEAPYEAR(year))
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days ++;
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days += readrtc(RTC_DAY) - 1;
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yd = days;
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for (y = 1970; y < year; y++)
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days += DAYSPERYEAR + LEAPYEAR(y);
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sec = ((( days * 24 +
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readrtc(RTC_HRS)) * 60 +
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readrtc(RTC_MIN)) * 60 +
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readrtc(RTC_SEC));
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/* sec now contains the number of seconds, since Jan 1 1970,
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in the local time zone */
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sec += tz.tz_minuteswest * 60 + adjkerntz;
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|
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s = splclock();
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time.tv_sec = sec;
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splx(s);
|
|
return;
|
|
|
|
wrong_time:
|
|
printf("Invalid time in real time clock.\n");
|
|
printf("Check and reset the date immediately!\n");
|
|
}
|
|
|
|
/*
|
|
* Write system time back to RTC
|
|
*/
|
|
void
|
|
resettodr()
|
|
{
|
|
unsigned long tm;
|
|
int y, m, fd, r, s;
|
|
|
|
if (disable_rtc_set)
|
|
return;
|
|
|
|
s = splclock();
|
|
tm = time.tv_sec;
|
|
splx(s);
|
|
|
|
/* Disable RTC updates and interrupts. */
|
|
writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
|
|
|
|
/* Calculate local time to put in RTC */
|
|
|
|
tm -= tz.tz_minuteswest * 60 + adjkerntz;
|
|
|
|
writertc(RTC_SEC, int2bcd(tm%60)); tm /= 60; /* Write back Seconds */
|
|
writertc(RTC_MIN, int2bcd(tm%60)); tm /= 60; /* Write back Minutes */
|
|
writertc(RTC_HRS, int2bcd(tm%24)); tm /= 24; /* Write back Hours */
|
|
|
|
/* We have now the days since 01-01-1970 in tm */
|
|
writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
|
|
for (y=1970;; y++)
|
|
if ((tm - DAYSPERYEAR - LEAPYEAR(y)) > tm)
|
|
break;
|
|
else
|
|
tm -= DAYSPERYEAR + LEAPYEAR(y);
|
|
|
|
/* Now we have the years in y and the day-of-the-year in tm */
|
|
writertc(RTC_YEAR, int2bcd(y%100)); /* Write back Year */
|
|
#ifdef USE_RTC_CENTURY
|
|
writertc(RTC_CENTURY, int2bcd(y/100)); /* ... and Century */
|
|
#endif
|
|
if (LEAPYEAR(y) && (tm >= 31+29))
|
|
tm--; /* Subtract Feb-29 */
|
|
for (m=1;; m++)
|
|
if (tm - daysinmonth[m-1] > tm)
|
|
break;
|
|
else
|
|
tm -= daysinmonth[m-1];
|
|
|
|
writertc(RTC_MONTH, int2bcd(m)); /* Write back Month */
|
|
writertc(RTC_DAY, int2bcd(tm+1)); /* Write back Day */
|
|
|
|
/* Reenable RTC updates and interrupts. */
|
|
writertc(RTC_STATUSB, RTCSB_24HR | RTCSB_PINTR);
|
|
}
|
|
|
|
/*
|
|
* Start both clocks running.
|
|
*/
|
|
void
|
|
cpu_initclocks()
|
|
{
|
|
int diag;
|
|
|
|
stathz = RTC_NOPROFRATE;
|
|
profhz = RTC_PROFRATE;
|
|
|
|
/* Finish initializing 8253 timer 0. */
|
|
register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, clkintr,
|
|
&clk_imask, /* unit */ 0);
|
|
INTREN(IRQ0);
|
|
|
|
/* Initialize RTC. */
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
writertc(RTC_STATUSB, RTCSB_24HR);
|
|
diag = rtcin(RTC_DIAG);
|
|
if (diag != 0)
|
|
printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
|
|
register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, rtcintr,
|
|
&stat_imask, /* unit */ 0);
|
|
INTREN(IRQ8);
|
|
writertc(RTC_STATUSB, RTCSB_24HR | RTCSB_PINTR);
|
|
}
|
|
|
|
void
|
|
setstatclockrate(int newhz)
|
|
{
|
|
if (newhz == RTC_PROFRATE)
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
|
|
else
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
}
|