5010737b39
driver's i/o ops must be locked to avoid chaos. Extend the cambria bus tag to support ata and add a spin lock. The ata driver is hacked to use that instead of it's builtin hack for ixp425. Once the ata driver is fixed to not be confused about byte order we can generalize the cambria bus tag code and make it generally useful. While here take advantage of our being ixp435-specific to remove delays when switching between byte+word accesses and to eliminate the 2us delay for the uarts (the spin lock overhead looks to do this for us).
259 lines
6.8 KiB
C
259 lines
6.8 KiB
C
/*-
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* Copyright (c) 2009 Sam Leffler. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Bus space tag for devices on the Cambria expansion bus.
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* This interlocks accesses to allow the optional GPS+RS485 UART's
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* to share access with the CF-IDE adapter. Note this does not
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* slow the timing UART r/w ops because the lock operation does
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* this implicitly for us. Also note we do not DELAY after byte/word
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* chip select changes; this doesn't seem necessary (as required
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* for IXP425/Avila boards).
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*
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* XXX should make this generic so all expansion bus devices can
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* use it but probably not until we eliminate the ATA hacks
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <arm/xscale/ixp425/ixp425reg.h>
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#include <arm/xscale/ixp425/ixp425var.h>
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/* Prototypes for all the bus_space structure functions */
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bs_protos(exp);
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bs_protos(generic);
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struct expbus_softc {
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struct ixp425_softc *sc; /* bus space tag */
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struct mtx lock; /* i/o interlock */
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bus_size_t csoff; /* CS offset for 8/16 enable */
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};
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#define EXP_LOCK_INIT(exp) \
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mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN)
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#define EXP_LOCK_DESTROY(exp) \
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mtx_destroy(&(exp)->lock)
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#define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock)
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#define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock)
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/*
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* Enable/disable 16-bit ops on the expansion bus.
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*/
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static __inline void
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enable_16(struct ixp425_softc *sc, bus_size_t cs)
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{
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EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN);
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}
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static __inline void
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disable_16(struct ixp425_softc *sc, bus_size_t cs)
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{
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EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN);
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}
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static uint8_t
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cambria_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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uint8_t v;
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EXP_LOCK(exp);
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v = bus_space_read_1(sc->sc_iot, h, o);
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EXP_UNLOCK(exp);
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return v;
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}
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static void
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cambria_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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EXP_LOCK(exp);
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bus_space_write_1(sc->sc_iot, h, o, v);
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EXP_UNLOCK(exp);
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}
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static uint16_t
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cambria_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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uint16_t v;
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EXP_LOCK(exp);
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enable_16(sc, exp->csoff);
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v = bus_space_read_2(sc->sc_iot, h, o);
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disable_16(sc, exp->csoff);
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EXP_UNLOCK(exp);
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return v;
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}
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static void
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cambria_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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EXP_LOCK(exp);
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enable_16(sc, exp->csoff);
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bus_space_write_2(sc->sc_iot, h, o, v);
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disable_16(sc, exp->csoff);
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EXP_UNLOCK(exp);
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}
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static void
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cambria_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o,
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u_int16_t *d, bus_size_t c)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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EXP_LOCK(exp);
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enable_16(sc, exp->csoff);
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bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
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disable_16(sc, exp->csoff);
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EXP_UNLOCK(exp);
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}
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static void
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cambria_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
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const u_int16_t *d, bus_size_t c)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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EXP_LOCK(exp);
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enable_16(sc, exp->csoff);
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bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
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disable_16(sc, exp->csoff);
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EXP_UNLOCK(exp);
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}
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/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
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static void
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cambria_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
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u_int16_t *d, bus_size_t c)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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uint16_t v;
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bus_size_t i;
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EXP_LOCK(exp);
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enable_16(sc, exp->csoff);
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#if 1
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for (i = 0; i < c; i++) {
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v = bus_space_read_2(sc->sc_iot, h, o);
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d[i] = bswap16(v);
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}
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#else
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bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
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#endif
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disable_16(sc, exp->csoff);
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EXP_UNLOCK(exp);
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}
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static void
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cambria_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
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const u_int16_t *d, bus_size_t c)
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{
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struct expbus_softc *exp = t;
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struct ixp425_softc *sc = exp->sc;
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bus_size_t i;
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EXP_LOCK(exp);
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enable_16(sc, exp->csoff);
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#if 1
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for (i = 0; i < c; i++)
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bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
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#else
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bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
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#endif
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disable_16(sc, exp->csoff);
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EXP_UNLOCK(exp);
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}
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/* NB: we only define what's needed by ata+uart */
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struct bus_space cambria_exp_bs_tag = {
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/* mapping/unmapping */
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.bs_map = generic_bs_map,
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.bs_unmap = generic_bs_unmap,
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/* barrier */
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.bs_barrier = generic_bs_barrier,
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/* read (single) */
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.bs_r_1 = cambria_bs_r_1,
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.bs_r_2 = cambria_bs_r_2,
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/* write (single) */
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.bs_w_1 = cambria_bs_w_1,
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.bs_w_2 = cambria_bs_w_2,
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/* read multiple */
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.bs_rm_2 = cambria_bs_rm_2,
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.bs_rm_2_s = cambria_bs_rm_2_s,
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/* write multiple */
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.bs_wm_2 = cambria_bs_wm_2,
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.bs_wm_2_s = cambria_bs_wm_2_s,
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};
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void
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cambria_exp_bus_init(struct ixp425_softc *sc)
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{
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static struct expbus_softc c3; /* NB: no need to malloc */
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uint32_t cs3;
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KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
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c3.sc = sc;
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c3.csoff = EXP_TIMING_CS3_OFFSET;
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EXP_LOCK_INIT(&c3);
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cambria_exp_bs_tag.bs_cookie = &c3;
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cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
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/* XXX force slowest possible timings and byte mode */
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EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
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cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
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EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
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/* XXX force GPIO 3+4 for GPS+RS485 uarts */
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ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING);
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ixp425_set_gpio(sc, 4, GPIO_TYPE_EDG_RISING);
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}
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