65 lines
2.6 KiB
Diff
65 lines
2.6 KiB
Diff
Pull in r214802 from upstream llvm trunk (by Renato Golin):
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Allow CP10/CP11 operations on ARMv5/v6
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Those registers are VFP/NEON and vector instructions should be used instead,
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but old cores rely on those co-processors to enable VFP unwinding. This change
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was prompted by the libc++abi's unwinding routine and is also present in many
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legacy low-level bare-metal code that we ought to compile/assemble.
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Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.
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Pull in r214872 from upstream llvm trunk (by Renato Golin):
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Add tests for cp10/cp11 on ARMv5/6
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Tests for ARMv7/8 are already on diagnostics.s
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This enables assembling certain ARM instructions used in libgcc.
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Introduced here: http://svnweb.freebsd.org/changeset/base/275265
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Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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===================================================================
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--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -3118,9 +3118,10 @@ static int MatchCoprocessorOperandName(StringRef N
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return -1;
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switch (Name[1]) {
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default: return -1;
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- // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
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- case '0': return CoprocOp == 'p'? -1: 10;
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- case '1': return CoprocOp == 'p'? -1: 11;
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+ // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
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+ // However, old cores (v5/v6) did use them in that way.
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+ case '0': return 10;
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+ case '1': return 11;
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case '2': return 12;
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case '3': return 13;
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case '4': return 14;
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@@ -3177,6 +3178,9 @@ ARMAsmParser::parseCoprocNumOperand(OperandVector
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int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
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if (Num == -1)
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return MatchOperand_NoMatch;
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+ // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
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+ if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
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+ return MatchOperand_NoMatch;
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Parser.Lex(); // Eat identifier token.
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Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
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Index: test/MC/ARM/coproc-diag.s
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===================================================================
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--- test/MC/ARM/coproc-diag.s
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+++ test/MC/ARM/coproc-diag.s
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@@ -0,0 +1,10 @@
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+# Special test to make sure we don't error on VFP co-proc access
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+@ RUN: llvm-mc -triple=armv5 < %s | FileCheck %s
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+@ RUN: llvm-mc -triple=armv6 < %s | FileCheck %s
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+
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+ @ p10 and p11 are reserved for NEON, but accessible on v5/v6
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+ ldc p10, cr0, [r0], {0x20}
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+ ldc2 p11, cr0, [r0], {0x21}
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+ ldcl p11, cr0, [r0], {0x20}
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+
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+@ CHECK-NOT: error: invalid operand for instruction
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