Andrew Turner 405ada37fb Add support for the uart classes to set their default register shift value. ...

This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.

This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.

MFC after:	1 week

2015-04-11 17:16:23 +00:00

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board_ln2410sbc.c

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files.s3c2xx0

Build the cpufunc_asm_* files based on the cpu type, not which config file

2015-03-29 22:43:39 +00:00

s3c2xx0board.h

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s3c2xx0reg.h

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s3c2xx0var.h

Use the base arm bus_space instead of an identical local copy.

2015-01-21 04:28:19 +00:00

s3c24x0_clk.c

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s3c24x0_machdep.c

Remove the bootconfig parsing. We never used it and always passed either an

2015-03-29 20:37:28 +00:00

s3c24x0_rtc.c

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s3c24x0.c

Use the base arm bus_space instead of an identical local copy.

2015-01-21 04:28:19 +00:00

s3c24x0reg.h

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s3c24x0var.h

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s3c2410reg.h

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s3c2410var.h

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s3c2440reg.h

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std.ln2410sbc

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std.s3c2410

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uart_bus_s3c2410.c

Move the uart_class definitions and fdt compat data into the individual

2015-03-07 15:24:15 +00:00

uart_cpu_s3c2410.c

Move the uart_class definitions and fdt compat data into the individual

2015-03-07 15:24:15 +00:00

uart_dev_s3c2410.c

Add support for the uart classes to set their default register shift value.

2015-04-11 17:16:23 +00:00

uart_dev_s3c2410.h

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