437 lines
12 KiB
C
437 lines
12 KiB
C
/*-
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* Copyright (c) 2000 - 2003 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SYS_ATA_H_
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#define _SYS_ATA_H_
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#include <sys/ioccom.h>
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#define ATAPI_PSIZE_12 0 /* 12 bytes */
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#define ATAPI_PSIZE_16 1 /* 16 bytes */
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#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
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#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
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#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
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#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
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#define ATAPI_TYPE_TAPE 1 /* streaming tape */
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#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
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#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
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#define ATA_PROTO_ATA 0
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#define ATA_PROTO_ATAPI 1
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#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
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#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
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#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
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#define ATA_FLAG_54_58 1 /* words 54-58 valid */
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#define ATA_FLAG_64_70 2 /* words 64-70 valid */
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#define ATA_FLAG_88 4 /* word 88 valid */
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/* ATA/ATAPI device parameter information */
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struct ata_params {
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*000*/ u_int16_t packet_size :2; /* packet command size */
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u_int16_t incomplete :1;
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u_int16_t :2;
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u_int16_t drq_type :2; /* DRQ type */
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u_int16_t removable :1; /* device is removable */
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u_int16_t type :5; /* device type */
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u_int16_t :2;
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u_int16_t cmd_protocol :1; /* command protocol */
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#else
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u_int16_t cmd_protocol :1; /* command protocol */
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u_int16_t :2;
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u_int16_t type :5; /* device type */
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u_int16_t removable :1; /* device is removable */
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u_int16_t drq_type :2; /* DRQ type */
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u_int16_t :2;
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u_int16_t incomplete :1;
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u_int16_t packet_size :2; /* packet command size */
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#endif
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/*001*/ u_int16_t cylinders; /* # of cylinders */
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u_int16_t reserved2;
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/*003*/ u_int16_t heads; /* # heads */
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u_int16_t obsolete4;
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u_int16_t obsolete5;
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/*006*/ u_int16_t sectors; /* # sectors/track */
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/*007*/ u_int16_t vendor7[3];
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/*010*/ u_int8_t serial[20]; /* serial number */
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u_int16_t retired20;
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u_int16_t retired21;
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u_int16_t obsolete22;
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/*023*/ u_int8_t revision[8]; /* firmware revision */
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/*027*/ u_int8_t model[40]; /* model name */
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*047*/ u_int16_t sectors_intr:8; /* sectors per interrupt */
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u_int16_t :8;
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#else
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u_int16_t :8;
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u_int16_t sectors_intr:8; /* sectors per interrupt */
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#endif
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/*048*/ u_int16_t usedmovsd; /* double word read/write? */
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*049*/ u_int16_t retired49:8;
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u_int16_t support_dma :1; /* DMA supported */
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u_int16_t support_lba :1; /* LBA supported */
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u_int16_t disable_iordy :1; /* IORDY may be disabled */
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u_int16_t support_iordy :1; /* IORDY supported */
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u_int16_t softreset :1; /* needs softreset when busy */
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u_int16_t stdby_ovlap :1; /* standby/overlap supported */
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u_int16_t support_queueing:1; /* supports queuing overlap */
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u_int16_t support_idma :1; /* interleaved DMA supported */
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/*050*/ u_int16_t device_stdby_min:1;
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u_int16_t :13;
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u_int16_t capability_one:1;
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u_int16_t capability_zero:1;
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/*051*/ u_int16_t vendor51:8;
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u_int16_t retired_piomode:8; /* PIO modes 0-2 */
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/*052*/ u_int16_t vendor52:8;
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u_int16_t retired_dmamode:8; /* DMA modes, not ATA-3 */
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#else
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u_int16_t support_idma :1; /* interleaved DMA supported */
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u_int16_t support_queueing:1; /* supports queuing overlap */
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u_int16_t stdby_ovlap :1; /* standby/overlap supported */
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u_int16_t softreset :1; /* needs softreset when busy */
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u_int16_t support_iordy :1; /* IORDY supported */
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u_int16_t disable_iordy :1; /* IORDY may be disabled */
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u_int16_t support_lba :1; /* LBA supported */
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u_int16_t support_dma :1; /* DMA supported */
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u_int16_t retired49:8;
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u_int16_t capability_zero:1;
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u_int16_t capability_one:1;
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u_int16_t :13;
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u_int16_t device_stdby_min:1;
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u_int16_t retired_piomode:8; /* PIO modes 0-2 */
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u_int16_t vendor51:8;
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u_int16_t retired_dmamode:8; /* DMA modes, not ATA-3 */
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u_int16_t vendor52:8;
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#endif
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/*053*/ u_int16_t atavalid; /* fields valid */
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u_int16_t obsolete54[5];
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*059*/ u_int16_t multi_count:8;
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u_int16_t multi_valid:1;
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u_int16_t :7;
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#else
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u_int16_t :7;
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u_int16_t multi_valid:1;
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u_int16_t multi_count:8;
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#endif
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/*060*/ u_int16_t lba_size_1;
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u_int16_t lba_size_2;
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u_int16_t obsolete62;
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/*063*/ u_int16_t mwdmamodes; /* multiword DMA modes */
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/*064*/ u_int16_t apiomodes; /* advanced PIO modes */
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/*065*/ u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
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/*066*/ u_int16_t mwdmarec; /* rec. M/W DMA time ns */
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/*067*/ u_int16_t pioblind; /* min. PIO cycle w/o flow */
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/*068*/ u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
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u_int16_t reserved69;
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u_int16_t reserved70;
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/*071*/ u_int16_t rlsovlap; /* rel time (us) for overlap */
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/*072*/ u_int16_t rlsservice; /* rel time (us) for service */
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u_int16_t reserved73;
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u_int16_t reserved74;
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*075*/ u_int16_t queuelen:5;
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u_int16_t :11;
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#else
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u_int16_t :11;
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u_int16_t queuelen:5;
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#endif
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u_int16_t reserved76;
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u_int16_t reserved77;
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u_int16_t reserved78;
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u_int16_t reserved79;
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/*080*/ u_int16_t version_major;
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/*081*/ u_int16_t version_minor;
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struct {
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*082/085*/ u_int16_t smart:1;
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u_int16_t security:1;
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u_int16_t removable:1;
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u_int16_t power_mngt:1;
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u_int16_t packet:1;
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u_int16_t write_cache:1;
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u_int16_t look_ahead:1;
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u_int16_t release_irq:1;
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u_int16_t service_irq:1;
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u_int16_t reset:1;
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u_int16_t protected:1;
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u_int16_t :1;
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u_int16_t write_buffer:1;
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u_int16_t read_buffer:1;
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u_int16_t nop:1;
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u_int16_t :1;
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/*083/086*/ u_int16_t microcode:1;
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u_int16_t queued:1;
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u_int16_t cfa:1;
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u_int16_t apm:1;
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u_int16_t notify:1;
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u_int16_t standby:1;
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u_int16_t spinup:1;
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u_int16_t :1;
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u_int16_t max_security:1;
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u_int16_t auto_acoustic:1;
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u_int16_t address48:1;
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u_int16_t config_overlay:1;
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u_int16_t flush_cache:1;
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u_int16_t flush_cache48:1;
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u_int16_t support_one:1;
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u_int16_t support_zero:1;
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/*084/087*/ u_int16_t smart_error_log:1;
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u_int16_t smart_self_test:1;
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u_int16_t media_serial_no:1;
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u_int16_t media_card_pass:1;
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u_int16_t streaming:1;
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u_int16_t logging:1;
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u_int16_t :8;
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u_int16_t extended_one:1;
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u_int16_t extended_zero:1;
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#else
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u_int16_t :1;
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u_int16_t nop:1;
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u_int16_t read_buffer:1;
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u_int16_t write_buffer:1;
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u_int16_t :1;
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u_int16_t protected:1;
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u_int16_t reset:1;
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u_int16_t service_irq:1;
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u_int16_t release_irq:1;
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u_int16_t look_ahead:1;
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u_int16_t write_cache:1;
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u_int16_t packet:1;
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u_int16_t power_mngt:1;
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u_int16_t removable:1;
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u_int16_t security:1;
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u_int16_t smart:1;
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u_int16_t support_zero:1;
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u_int16_t support_one:1;
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u_int16_t flush_cache48:1;
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u_int16_t flush_cache:1;
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u_int16_t config_overlay:1;
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u_int16_t address48:1;
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u_int16_t auto_acoustic:1;
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u_int16_t max_security:1;
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u_int16_t :1;
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u_int16_t spinup:1;
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u_int16_t standby:1;
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u_int16_t notify:1;
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u_int16_t apm:1;
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u_int16_t cfa:1;
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u_int16_t queued:1;
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u_int16_t microcode:1;
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u_int16_t extended_zero:1;
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u_int16_t extended_one:1;
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u_int16_t :8;
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u_int16_t logging:1;
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u_int16_t streaming:1;
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u_int16_t media_card_pass:1;
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u_int16_t media_serial_no:1;
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u_int16_t smart_self_test:1;
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u_int16_t smart_error_log:1;
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#endif
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} support, enabled;
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/*088*/ u_int16_t udmamodes; /* UltraDMA modes */
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/*089*/ u_int16_t erase_time;
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/*090*/ u_int16_t enhanced_erase_time;
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/*091*/ u_int16_t apm_value;
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/*092*/ u_int16_t master_passwd_revision;
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#if BYTE_ORDER == LITTLE_ENDIAN
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/*093*/ u_int16_t hwres_master :8;
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u_int16_t hwres_slave :5;
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u_int16_t hwres_cblid :1;
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u_int16_t hwres_valid:2;
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/*094*/ u_int16_t current_acoustic:8;
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u_int16_t vendor_acoustic:8;
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#else
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u_int16_t hwres_valid:2;
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u_int16_t hwres_cblid :1;
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u_int16_t hwres_slave :5;
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u_int16_t hwres_master :8;
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u_int16_t vendor_acoustic:8;
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u_int16_t current_acoustic:8;
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#endif
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/*095*/ u_int16_t stream_min_req_size;
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/*096*/ u_int16_t stream_transfer_time;
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/*097*/ u_int16_t stream_access_latency;
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/*098*/ u_int32_t stream_granularity;
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/*100*/ u_int16_t lba_size48_1;
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u_int16_t lba_size48_2;
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u_int16_t lba_size48_3;
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u_int16_t lba_size48_4;
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u_int16_t reserved104[23];
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/*127*/ u_int16_t removable_status;
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/*128*/ u_int16_t security_status;
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u_int16_t reserved129[31];
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/*160*/ u_int16_t cfa_powermode1;
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u_int16_t reserved161[14];
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/*176*/ u_int16_t media_serial[30];
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u_int16_t reserved206[49];
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/*255*/ u_int16_t integrity;
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};
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#define ATA_MODE_MASK 0x0f
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#define ATA_DMA_MASK 0xf0
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#define ATA_PIO 0x00
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#define ATA_PIO0 0x08
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#define ATA_PIO1 0x09
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#define ATA_PIO2 0x0a
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#define ATA_PIO3 0x0b
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#define ATA_PIO4 0x0c
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#define ATA_PIO_MAX 0x0f
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#define ATA_DMA 0x10
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#define ATA_WDMA0 0x20
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#define ATA_WDMA1 0x21
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#define ATA_WDMA2 0x22
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#define ATA_UDMA0 0x40
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#define ATA_UDMA1 0x41
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#define ATA_UDMA2 0x42
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#define ATA_UDMA3 0x43
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#define ATA_UDMA4 0x44
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#define ATA_UDMA5 0x45
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#define ATA_UDMA6 0x46
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#define ATA_SA150 0x47
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#define ATA_DMA_MAX 0x4f
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struct ata_cmd {
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int channel;
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int device;
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int cmd;
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#define ATAGPARM 1
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#define ATAGMODE 2
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#define ATASMODE 3
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#define ATAREINIT 4
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#define ATAATTACH 5
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#define ATADETACH 6
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#define ATAPICMD 7
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#define ATARAIDREBUILD 8
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#define ATARAIDCREATE 9
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#define ATARAIDDELETE 10
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#define ATARAIDSTATUS 11
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#define ATAENCSTAT 12
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#define ATAGMAXCHANNEL 13
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#define ATARAIDADDSPARE 14
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union {
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struct {
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int mode[2];
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} mode;
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struct {
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int type[2];
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char name[2][32];
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struct ata_params params[2];
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} param;
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struct raid_setup {
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int type;
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#define AR_RAID0 1
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#define AR_RAID1 2
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#define AR_SPAN 4
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int total_disks;
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int disks[16];
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int interleave;
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int unit;
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} raid_setup;
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struct {
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int disk;
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} raid_spare;
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struct raid_status {
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int type;
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int total_disks;
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int disks[16];
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int interleave;
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int status;
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#define AR_READY 1
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#define AR_DEGRADED 2
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#define AR_REBUILDING 4
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int progress;
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} raid_status;
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struct {
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int fan;
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int temp;
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int v05;
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int v12;
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} enclosure;
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struct {
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char ccb[16];
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caddr_t data;
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int count;
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int flags;
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#define ATAPI_CMD_CTRL 0x00
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#define ATAPI_CMD_READ 0x01
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#define ATAPI_CMD_WRITE 0x02
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int timeout;
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int error;
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char sense_data[18];
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} atapi;
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int maxchan;
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} u;
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};
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#define IOCATA _IOWR('a', 1, struct ata_cmd)
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#endif /* _SYS_ATA_H_ */
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