3364e8aea9
o Replace __riscv64 with (__riscv && __riscv_xlen == 64) This is required to support new GCC 7.1 compiler. This is compatible with current GCC 6.1 compiler. RISC-V is extensible ISA and the idea here is to have built-in define per each extension, so together with __riscv we will have some subset of these as well (depending on -march string passed to compiler): __riscv_compressed __riscv_atomic __riscv_mul __riscv_div __riscv_muldiv __riscv_fdiv __riscv_fsqrt __riscv_float_abi_soft __riscv_float_abi_single __riscv_float_abi_double __riscv_cmodel_medlow __riscv_cmodel_medany __riscv_cmodel_pic __riscv_xlen Reviewed by: ngie Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11901
352 lines
11 KiB
Groff
352 lines
11 KiB
Groff
.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved.
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.\"
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.\" This documentation was created by Ed Maste under sponsorship of
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.\" The FreeBSD Foundation.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd May 16, 2017
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.Dt ARCH 7
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.Os
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.Sh NAME
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.Nm arch
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.Nd Architecture-specific details
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.Sh DESCRIPTION
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Differences between CPU architectures and platforms supported by
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.Fx .
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.Ss Introduction
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This document is a quick reference of key ABI details of
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.Fx
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architecture ports.
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For full details consult the processor-specific ABI supplement
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documentation.
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.Pp
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If not explicitly mentioned, sizes are in bytes.
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The architecture details in this document apply to
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.Fx 10.0
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and later, unless otherwise noted.
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.Pp
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.Fx
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uses a flat address space.
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Variables of types
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.Vt unsigned long ,
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.Vt uintptr_t ,
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and
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.Vt size_t
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and pointers all have the same representation.
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.Pp
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In order to maximize compatibility with future pointer integrity mechanisms,
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manipulations of pointers as integers should be performed via
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.Vt uintptr_t
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or
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.Vt intptr_t
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and no other types.
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In particular,
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.Vt long
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and
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.Vt ptrdiff_t
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should be avoided.
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.Pp
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On some architectures, e.g.
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.Dv sparc64 ,
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.Dv powerpc
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and AIM variants of
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.Dv powerpc64 ,
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the kernel uses a separate address space.
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On other architectures, kernel and a user mode process share a
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single address space.
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The kernel is located at the highest addresses.
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.Pp
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On each architecture, the main user mode thread's stack starts near
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the highest user address and grows down.
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.Pp
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.Fx
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architecture support varies by release.
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This table shows the first
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.Fx
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release to support each architecture, and, for discontinued
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architectures, the final release.
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.Pp
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.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
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.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
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.It alpha Ta 3.2 Ta 6.4
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.It amd64 Ta 5.1
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.It arm Ta 6.0
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.It armeb Ta 8.0
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.It armv6 Ta 10.0
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.It arm64 Ta 11.0
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.It ia64 Ta 5.0 Ta 10.x
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.It i386 Ta 1.0
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.It mips Ta 8.0
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.It mipsel Ta 9.0
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.It mipselhf Ta 12.0
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.It mipshf Ta 12.0
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.It mipsn32 Ta 9.0
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.It mips64 Ta 9.0
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.It mips64el Ta 9.0
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.It mips64elhf Ta 12.0
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.It mips64hf Ta 12.0
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.It pc98 Ta 2.2 Ta 11.x
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.It powerpc Ta 6.0
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.It powerpcspe Ta 12.0
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.It powerpc64 Ta 6.0
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.It riscv64 Ta 12.0
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.It riscv64sf Ta 12.0
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.It sparc64 Ta 5.0
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.El
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.Ss Type sizes
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All
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.Fx
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architectures use some variant of the ELF (see
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.Xr elf 5 )
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.Sy Application Binary Interface
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(ABI) for the machine processor.
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All supported ABIs can be divided into two groups:
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.Bl -tag -width "Dv ILP32"
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.It Dv ILP32
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.Vt int ,
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.Vt long ,
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.Vt void *
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types machine representations all have 4-byte size.
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.It Dv LP64
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.Vt int
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type machine representation uses 4 bytes,
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while
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.Vt long
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and
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.Vt void *
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are 8 bytes.
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.El
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Compilers define the
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.Dv _LP64
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symbol when compiling for an
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.Dv LP64
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ABI.
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.Pp
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Some machines support more that one
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.Fx
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ABI.
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Typically these are 64-bit machines, where the
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.Dq native
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.Dv LP64
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execution environment is accompanied by the
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.Dq legacy
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.Dv ILP32
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environment, which was historical 32-bit predecessor for 64-bit evolution.
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Examples are:
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.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
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.It Sy LP64 Ta Sy ILP32 counterpart
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.It Dv amd64 Ta Dv i386
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.It Dv powerpc64 Ta Dv powerpc
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.It Dv mips64* Ta Dv mips*
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.El
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.Dv arm64
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currently does not support execution of
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.Dv armv6
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binaries, even if the CPU implements
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.Dv AArch32
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execution state.
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.Pp
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On all supported architectures:
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.Bl -column -offset -indent "long long" "Size"
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.It Sy Type Ta Sy Size
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.It short Ta 2
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.It int Ta 4
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.It long Ta sizeof(void*)
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.It long long Ta 8
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.It float Ta 4
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.It double Ta 8
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.El
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Integers are represented in two's complement.
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Alignment of integer and pointer types is natural, that is,
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the address of the variable must be congruent to zero modulo the type size.
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Most ILP32 ABIs, except
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.Dv arm ,
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require only 4-byte alignment for 64-bit integers.
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.Pp
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Machine-dependent type sizes:
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.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
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.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
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.It amd64 Ta 8 Ta 16 Ta 8
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.It arm Ta 4 Ta 8 Ta 8
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.It armeb Ta 4 Ta 8 Ta 8
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.It armv6 Ta 4 Ta 8 Ta 8
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.It arm64 Ta 8 Ta 16 Ta 8
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.It i386 Ta 4 Ta 12 Ta 4
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.It mips Ta 4 Ta 8 Ta 8
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.It mipsel Ta 4 Ta 8 Ta 8
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.It mipselhf Ta 4 Ta 8 Ta 8
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.It mipshf Ta 4 Ta 8 Ta 8
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.It mipsn32 Ta 4 Ta 8 Ta 8
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.It mips64 Ta 8 Ta 8 Ta 8
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.It mips64el Ta 8 Ta 8 Ta 8
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.It mips64elhf Ta 8 Ta 8 Ta 8
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.It mips64hf Ta 8 Ta 8 Ta 8
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.It powerpc Ta 4 Ta 8 Ta 8
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.It powerpcspe Ta 4 Ta 8 Ta 8
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.It powerpc64 Ta 8 Ta 8 Ta 8
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.It riscv64 Ta 8 Ta 16 Ta 8
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.It riscv64sf Ta 8 Ta 16 Ta 8
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.It sparc64 Ta 8 Ta 16 Ta 8
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.El
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.Pp
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.Sy time_t
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is 8 bytes on all supported architectures except i386 and 32-bit
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variants of powerpc.
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.Ss Endianness and Char Signedness
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.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
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.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
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.It amd64 Ta little Ta signed
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.It arm Ta little Ta unsigned
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.It armeb Ta big Ta unsigned
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.It armv6 Ta little Ta unsigned
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.It arm64 Ta little Ta unsigned
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.It i386 Ta little Ta signed
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.It mips Ta big Ta signed
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.It mipsel Ta little Ta signed
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.It mipselhf Ta little Ta signed
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.It mipshf Ta big Ta signed
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.It mipsn32 Ta big Ta signed
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.It mips64 Ta big Ta signed
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.It mips64el Ta little Ta signed
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.It mips64elhf Ta little Ta signed
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.It mips64hf Ta big Ta signed
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.It powerpc Ta big Ta unsigned
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.It powerpcspe Ta big Ta unsigned
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.It powerpc64 Ta big Ta unsigned
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.It riscv64 Ta little Ta signed
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.It riscv64sf Ta little Ta signed
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.It sparc64 Ta big Ta signed
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.El
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.Ss Page Size
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.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
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.It Sy Architecture Ta Sy Page Sizes
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.It amd64 Ta 4K, 2M, 1G
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.It arm Ta 4K
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.It armeb Ta 4K
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.It armv6 Ta 4K, 1M
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.It arm64 Ta 4K, 2M, 1G
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.It i386 Ta 4K, 2M (PAE), 4M
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.It mips Ta 4K
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.It mipsel Ta 4K
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.It mipselhf Ta 4K
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.It mipshf Ta 4K
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.It mipsn32 Ta 4K
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.It mips64 Ta 4K
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.It mips64el Ta 4K
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.It mips64elhf Ta 4K
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.It mips64hf Ta 4K
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.It powerpc Ta 4K
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.It powerpcspe Ta 4K
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.It powerpc64 Ta 4K
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.It riscv64 Ta 4K
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.It riscv64sf Ta 4K
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.It sparc64 Ta 8K
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.El
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.Ss Floating Point
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.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
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.It Sy Architecture Ta Sy float, double Ta Sy long double
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.It amd64 Ta hard Ta hard, 80 bit
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.It arm Ta soft Ta soft, double precision
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.It armeb Ta soft Ta soft, double precision
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.It armv6 Ta hard(1) Ta hard, double precision
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.It arm64 Ta hard Ta soft, quad precision
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.It i386 Ta hard Ta hard, 80 bit
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.It mips Ta soft Ta identical to double
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.It mipsel Ta soft Ta identical to double
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.It mipselhf Ta hard Ta identical to double
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.It mipshf Ta hard Ta identical to double
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.It mipsn32 Ta soft Ta identical to double
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.It mips64 Ta soft Ta identical to double
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.It mips64el Ta soft Ta identical to double
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.It mips64elhf Ta hard Ta identical to double
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.It mips64hf Ta hard Ta identical to double
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.It powerpc Ta hard Ta hard, double precision
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.It powerpcspe Ta hard Ta hard, double precision
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.It powerpc64 Ta hard Ta hard, double precision
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.It riscv64 Ta hard Ta hard, double precision
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.It riscv64sf Ta soft Ta soft, double precision
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.It sparc64 Ta hard Ta hard, quad precision
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.El
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.Pp
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(1) Prior to
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.Fx 11.0 ,
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armv6 used the softfp ABI even though it supported only processors
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with a floating point unit.
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.Ss Predefined Macros
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The compiler provides a number of predefined macros.
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Some of these provide architecture-specific details and are explained below.
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Other macros, including those required by the language standard, are not
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included here.
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.Pp
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The full set of predefined macros can be obtained with this command:
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.Bd -literal -offset indent
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cc -x c -dM -E /dev/null
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.Ed
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.Pp
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Common type size and endianness macros:
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.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
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.It Sy Macro Ta Sy Meaning
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.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
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.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
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.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
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.Dv PDP11_ENDIAN
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is not used on
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.Fx .
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.El
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.Pp
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Architecture-specific macros:
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.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
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.It Sy Architecture Ta Sy Predefined macros
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.It amd64 Ta Dv __amd64__, Dv __x86_64__
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.It arm Ta Dv __arm__
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.It armeb Ta Dv __arm__
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.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
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.It arm64 Ta Dv __aarch64__
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.It i386 Ta Dv __i386__
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.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
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.It mipsel Ta Dv __mips__, Dv __mips_o32
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.It mipselhf Ta Dv __mips__, Dv __mips_o32
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.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
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.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
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.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
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.It mips64el Ta Dv __mips__, Dv __mips_n64
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.It mips64elhf Ta Dv __mips__, Dv __mips_n64
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.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
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.It powerpc Ta Dv __powerpc__
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.It powerpcspe Ta Dv __powerpc__, Dv __SPE__
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.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
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.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
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.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
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.It sparc64 Ta Dv __sparc64__
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.El
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.Sh SEE ALSO
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.Xr src.conf 5 ,
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.Xr build 7
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.Sh HISTORY
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An
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.Nm
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manual page appeared in
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.Fx 12 .
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