2aaca76675
register, in addition to configuring it as input with the pinmux driver. There was a control register bit commented as "no desc in datasheet". A later revision of the manual reveals the bit to be an input/output control for the timer pin. In addition to configuring capture or pulse mode, you apparently have to separately configure the pin direction in the timer control register. Before this change, the timer block was apparently driving a signal onto a pad configured by pinmux as input. Capture mode still accidentally worked for me during testing because I was using a very strong signal source that just out-muscled the weaker drive from the misconfigured pin.
77 lines
3.9 KiB
C
77 lines
3.9 KiB
C
/*-
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef AM335X_DMTREG_H
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#define AM335X_DMTREG_H
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#define AM335X_NUM_TIMERS 8
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#define DMT_TIDR 0x00 /* Identification Register */
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#define DMT_TIOCP_CFG 0x10 /* OCP Configuration Reg */
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#define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */
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#define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */
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#define DMT_IRQSTATUS_RAW 0x24 /* IRQSTATUS Raw Reg */
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#define DMT_IRQSTATUS 0x28 /* IRQSTATUS Reg */
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#define DMT_IRQENABLE_SET 0x2c /* IRQSTATUS Set Reg */
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#define DMT_IRQENABLE_CLR 0x30 /* IRQSTATUS Clear Reg */
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#define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */
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#define DMT_IRQ_MAT (1 << 0) /* IRQ: Match */
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#define DMT_IRQ_OVF (1 << 1) /* IRQ: Overflow */
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#define DMT_IRQ_TCAR (1 << 2) /* IRQ: Capture */
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#define DMT_IRQ_MASK (DMT_IRQ_TCAR | DMT_IRQ_OVF | DMT_IRQ_MAT)
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#define DMT_TCLR 0x38 /* Control Register */
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#define DMT_TCLR_START (1 << 0) /* Start timer */
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#define DMT_TCLR_AUTOLOAD (1 << 1) /* Auto-reload on overflow */
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#define DMT_TCLR_PRES_MASK (7 << 2) /* Prescaler mask */
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#define DMT_TCLR_PRES_ENABLE (1 << 5) /* Prescaler enable */
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#define DMT_TCLR_COMP_ENABLE (1 << 6) /* Compare enable */
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#define DMT_TCLR_PWM_HIGH (1 << 7) /* PWM default output high */
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#define DMT_TCLR_CAPTRAN_MASK (3 << 8) /* Capture transition mask */
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#define DMT_TCLR_CAPTRAN_NONE (0 << 8) /* Capture: none */
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#define DMT_TCLR_CAPTRAN_LOHI (1 << 8) /* Capture lo->hi transition */
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#define DMT_TCLR_CAPTRAN_HILO (2 << 8) /* Capture hi->lo transition */
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#define DMT_TCLR_CAPTRAN_BOTH (3 << 8) /* Capture both transitions */
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#define DMT_TCLR_TRGMODE_MASK (3 << 10) /* Trigger output mode mask */
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#define DMT_TCLR_TRGMODE_NONE (0 << 10) /* Trigger off */
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#define DMT_TCLR_TRGMODE_OVFL (1 << 10) /* Trigger on overflow */
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#define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */
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#define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */
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#define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */
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#define DMT_TCLR_GPO_CFG (1 << 14) /* Tmr pin conf, 0=out, 1=in */
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#define DMT_TCRR 0x3C /* Counter Register */
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#define DMT_TLDR 0x40 /* Load Reg */
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#define DMT_TTGR 0x44 /* Trigger Reg */
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#define DMT_TWPS 0x48 /* Write Posted Status Reg */
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#define DMT_TMAR 0x4C /* Match Reg */
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#define DMT_TCAR1 0x50 /* Capture Reg */
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#define DMT_TSICR 0x54 /* Synchr. Interface Ctrl Reg */
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#define DMT_TSICR_RESET (1 << 1) /* TSICR perform soft reset */
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#define DMT_TCAR2 0x48 /* Capture Reg */
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#endif /* AM335X_DMTREG_H */
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