42c24319a9
The newest ena-com HAL supports LLQv2 and introduces API changes. In order not to break the driver compilation it was updated/fixed in a following way: * Change version of the driver to 0.8.0 * Provide reset cause when triggering reset of the device * Reset device after attach fails * In the reset task free management irq after calling ena_down. Admin queue can still be used before ena_down is called, or when it is being handled * Do not reset device if ena_reset_task fails * Move call of the ena_com_dev_reset to the ena_down() routine - it should be called only if interface was up * Use different function for checking empty space on the sq ring (ena-com API change) * Fix typo on ENA_TX_CLEANUP_THRESHOLD * Change checking for EPERM with EOPNOTSUPP - change in the ena-com API * Minor style fixes Submitted by: Michal Krawczyk <mk@semihalf.com> Obtained from: Amazon.com, Inc. Semihalf Sponsored by: Amazon.com, Inc. Differential Revision: https://reviews.freebsd.org/D12143
187 lines
5.4 KiB
C
187 lines
5.4 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ENA_ETH_COM_H_
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#define ENA_ETH_COM_H_
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#include "ena_com.h"
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/* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */
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#define ENA_COMP_HEAD_THRESH 4
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struct ena_com_tx_ctx {
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struct ena_com_tx_meta ena_meta;
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struct ena_com_buf *ena_bufs;
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/* For LLQ, header buffer - pushed to the device mem space */
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void *push_header;
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enum ena_eth_io_l3_proto_index l3_proto;
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enum ena_eth_io_l4_proto_index l4_proto;
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u16 num_bufs;
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u16 req_id;
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/* For regular queue, indicate the size of the header
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* For LLQ, indicate the size of the pushed buffer
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*/
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u16 header_len;
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u8 meta_valid;
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u8 tso_enable;
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u8 l3_csum_enable;
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u8 l4_csum_enable;
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u8 l4_csum_partial;
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u8 df; /* Don't fragment */
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};
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struct ena_com_rx_ctx {
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struct ena_com_rx_buf_info *ena_bufs;
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enum ena_eth_io_l3_proto_index l3_proto;
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enum ena_eth_io_l4_proto_index l4_proto;
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bool l3_csum_err;
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bool l4_csum_err;
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/* fragmented packet */
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bool frag;
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u32 hash;
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u16 descs;
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int max_bufs;
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};
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int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
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struct ena_com_tx_ctx *ena_tx_ctx,
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int *nb_hw_desc);
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int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
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struct ena_com_io_sq *io_sq,
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struct ena_com_rx_ctx *ena_rx_ctx);
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int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
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struct ena_com_buf *ena_buf,
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u16 req_id);
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int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
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static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
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struct ena_eth_io_intr_reg *intr_reg)
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{
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ENA_REG_WRITE32(io_cq->bus, intr_reg->intr_control, io_cq->unmask_reg);
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}
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static inline int ena_com_free_desc(struct ena_com_io_sq *io_sq)
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{
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u16 tail, next_to_comp, cnt;
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next_to_comp = io_sq->next_to_comp;
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tail = io_sq->tail;
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cnt = tail - next_to_comp;
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return io_sq->q_depth - 1 - cnt;
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}
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/* Check if the submission queue has enough space to hold required_buffers */
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static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
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u16 required_buffers)
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{
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int temp;
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if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
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return ena_com_free_desc(io_sq) >= required_buffers;
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/* This calculation doesn't need to be 100% accurate. So to reduce
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* the calculation overhead just Subtract 2 lines from the free descs
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* (one for the header line and one to compensate the devision
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* down calculation.
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*/
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temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;
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return ena_com_free_desc(io_sq) > temp;
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}
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static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
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{
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u16 tail;
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tail = io_sq->tail;
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ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n",
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io_sq->qid, tail);
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ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
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return 0;
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}
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static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
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{
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u16 unreported_comp, head;
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bool need_update;
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head = io_cq->head;
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unreported_comp = head - io_cq->last_head_update;
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need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
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if (io_cq->cq_head_db_reg && need_update) {
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ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n",
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io_cq->qid, head);
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ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);
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io_cq->last_head_update = head;
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}
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return 0;
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}
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static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
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u8 numa_node)
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{
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struct ena_eth_io_numa_node_cfg_reg numa_cfg;
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if (!io_cq->numa_node_cfg_reg)
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return;
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numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
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| ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
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ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
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}
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static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)
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{
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io_sq->next_to_comp += elem;
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}
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#if defined(__cplusplus)
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}
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#endif
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#endif /* ENA_ETH_COM_H_ */
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