52cdf0b123
Use the same cache terminology as the ARM docs in comments. No functional changes. Use armv7 TLB flush code, not arm11, for cortex-a processors. Exynos/ Arndale... - Disable debugging by default. - Add display-related and clk devices to the tree - Prevent resources intersection with EHCI driver - Add display-related and clk devices to the tree - Prevent resources intersection with EHCI driver - Add driver for Display Controller. - Add support for Samsung Chromebook (ARM Cortex A15 machine). - Rename mct and ehci drivers files to match common naming.
41 lines
1.8 KiB
C
41 lines
1.8 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define READ4(_sc, _reg) \
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bus_space_read_4(_sc->bst, _sc->bsh, _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
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#define READ2(_sc, _reg) \
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bus_space_read_2(_sc->bst, _sc->bsh, _reg)
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#define WRITE2(_sc, _reg, _val) \
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bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
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#define READ1(_sc, _reg) \
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bus_space_read_1(_sc->bst, _sc->bsh, _reg)
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#define WRITE1(_sc, _reg, _val) \
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bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val)
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