52cdf0b123
Use the same cache terminology as the ARM docs in comments. No functional changes. Use armv7 TLB flush code, not arm11, for cortex-a processors. Exynos/ Arndale... - Disable debugging by default. - Add display-related and clk devices to the tree - Prevent resources intersection with EHCI driver - Add display-related and clk devices to the tree - Prevent resources intersection with EHCI driver - Add driver for Display Controller. - Add support for Samsung Chromebook (ARM Cortex A15 machine). - Rename mct and ehci drivers files to match common naming.
140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/*-
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* Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This module just enables Exynos MCT, so ARMv7 Generic Timer will works
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#define MCT_CTRL_START (1 << 8)
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#define MCT_CTRL (0x240)
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#define MCT_WRITE_STAT (0x24C)
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struct arm_tmr_softc {
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struct resource *tmr_res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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};
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static struct resource_spec arm_tmr_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Timer registers */
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{ -1, 0 }
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};
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static int
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arm_tmr_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "exynos,mct"))
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return (ENXIO);
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device_set_desc(dev, "Exynos MPCore Timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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arm_tmr_attach(device_t dev)
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{
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struct arm_tmr_softc *sc;
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int reg, i;
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int mask;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Timer interface */
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sc->bst = rman_get_bustag(sc->tmr_res[0]);
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sc->bsh = rman_get_bushandle(sc->tmr_res[0]);
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reg = bus_space_read_4(sc->bst, sc->bsh, MCT_CTRL);
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reg |= MCT_CTRL_START;
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bus_space_write_4(sc->bst, sc->bsh, MCT_CTRL, reg);
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mask = (1 << 16);
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/* Wait 10 times until written value is applied */
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for (i = 0; i < 10; i++) {
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reg = bus_space_read_4(sc->bst, sc->bsh, MCT_WRITE_STAT);
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if (reg & mask) {
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bus_space_write_4(sc->bst, sc->bsh,
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MCT_WRITE_STAT, mask);
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return (0);
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}
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cpufunc_nullop();
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}
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/* NOTREACHED */
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panic("Can't enable timer\n");
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}
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static device_method_t arm_tmr_methods[] = {
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DEVMETHOD(device_probe, arm_tmr_probe),
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DEVMETHOD(device_attach, arm_tmr_attach),
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{ 0, 0 }
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};
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static driver_t arm_tmr_driver = {
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"mct",
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arm_tmr_methods,
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sizeof(struct arm_tmr_softc),
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};
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static devclass_t arm_tmr_devclass;
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DRIVER_MODULE(mct, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
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