85de9f54f8
the ncr53c9x.c core where it actually belongs so future front-ends
don't need to add it.
o Use the correct OFW property when looking for the initiator ID of the
SBus device.
o Don't specify an alignment when creating the parent DMA tag for
SUNW,fas; their DMA engine doesn't require an alignment constraint
and it's no inherited by the child DMA tags anyway (which probably
is a bug though).
o Drop the superfluous sc_maxsync and use sc_minsync instead. The
former apparently was added due to a confusion with the maximum
frequency used in cam(4), which basically corresponds to the
inverse of minimum sync period.
o Merge ncr53c9x.c from NetBSD:
1.116: NCRDMA_SETUP() should be called before NCR_SET_COUNT() and
NCRCMD_DMA command in ncr53c9x_select().
1.125: free allocated resources on detach.
o Static'ize ncr53c9x_action(), ncr53c9x_init() and ncr53c9x_reset()
as these are not required outside of ncr53c9x.c.
o In ncr53c9x_attach() don't leak the device mutex in case attaching
fails.
o Register an asynchronous notification handler so in case cam(4)
reports a lost device we can cancel outstanding commands and
restore the default parameters for the target in question.
o For FAS366 correctly support 16-bit target IDs and let it know
that we use 32-bit transfers.
o Overhaul the negotiation of transfer settings. This includes
distinguishing between current and goal transfer settings of the
target so we can renegotiate their goal settings when necessary
and correcting the order in which tagged, wide and synchronous
transfers are negotiated.
o If we are requesting sense, force a renegotiation if we are
currently using anything different from asynchronous at 8 bit
as the target might have lost our transfer negotiations.
o In case of an XPT_RESET_BUS just directly call ncr53c9x_init()
instead of issuing a NCRCMD_RSTSCSI, which in turn will issue an
interrupt that is treated as an unexpected SCSI bus reset by
ncr53c9x_intr() and thus calls ncr53c9x_init(). Remove the now
no longer used ncr53c9x_scsi_reset().
o Correct an off-by-one error when setting cpi->max_lun.
o In replace printf(9) with device_printf(9) calls where appropriate
and in ncr53c9x_action() remove some unnecessarily verbose messages.
o In ncr53c9x_sched() use TAILQ_FOREACH() instead of reimplementing
it and consolidate two tagging-related target info checks into one.
o In ncr53c9x_done() set the CAM status to CAM_SCSI_STATUS_ERROR when
appropriate, respect CAM_DIS_AUTOSENSE and teach it to return SCSI
status information.
o In ncr53c9x_dequeue() ensure the tags are cleared.
o Use ulmin() instead of min() where appropriate.
o In ncr53c9x_msgout() consistently use the reset label.
o When we're interrupted during a data phase and the DMA engine is
still active, don't panic but reset the core and the DMA engine as
this should be sufficient. Also, the typical problem for triggering
this was the lack of renegotiation when requesting sense.
o Correctly handle DEVICE RESETs.
o Adapt the locking of esp(4) to MPSAFE cam(4). This includes moving
the calls of lsi64854_attach() to the bus front-ends so it can pass
the esp(4) mutex to bus_dma_tag_create(9).
o Change the LSI64854 driver to not create a DMA tag and map for the
Ethernet channel as le(4) will handle these on its own as well as
sync and unload the DMA maps for the SCSI and parallel port channel
after a DMA transfer.
o Cam(4)'ify some NetBSD-centric comments.
o Use bus_{read,write}_*(9) instead of bus_space_{read,write}_*(9)
and take advantage of rman_get_rid(9) in order to save some softc
members.
Reviewed by: scottl
MFC after: 1 month
291 lines
12 KiB
C
291 lines
12 KiB
C
/* $NetBSD: ncr53c9xreg.h,v 1.14 2005/02/27 00:27:02 perry Exp $ */
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/*-
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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/*
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* Register addresses, relative to some base address
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*/
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#define NCR_TCL 0x00 /* RW - Transfer Count Low */
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#define NCR_TCM 0x01 /* RW - Transfer Count Mid */
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#define NCR_TCH 0x0e /* RW - Transfer Count High */
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/* NOT on 53C90 */
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#define NCR_FIFO 0x02 /* RW - FIFO data */
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#define NCR_CMD 0x03 /* RW - Command (2 deep) */
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#define NCRCMD_DMA 0x80 /* DMA Bit */
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#define NCRCMD_NOP 0x00 /* No Operation */
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#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
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#define NCRCMD_RSTCHIP 0x02 /* Reset Chip */
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#define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
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#define NCRCMD_RESEL 0x40 /* Reselect Sequence */
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#define NCRCMD_SELNATN 0x41 /* Select without ATN */
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#define NCRCMD_SELATN 0x42 /* Select with ATN */
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#define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */
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#define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */
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#define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */
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#define NCRCMD_SELATN3 0x46 /* Select with ATN3 */
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#define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */
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#define NCRCMD_SNDMSG 0x20 /* Send Message */
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#define NCRCMD_SNDSTAT 0x21 /* Send Status */
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#define NCRCMD_SNDDATA 0x22 /* Send Data */
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#define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */
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#define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */
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#define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */
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#define NCRCMD_DISC 0x27 /* Disconnect */
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#define NCRCMD_RECMSG 0x28 /* Receive Message */
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#define NCRCMD_RECCMD 0x29 /* Receive Command */
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#define NCRCMD_RECDATA 0x2a /* Receive Data */
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#define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
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#define NCRCMD_ABORT 0x04 /* Target Abort DMA */
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#define NCRCMD_TRANS 0x10 /* Transfer Information */
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#define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
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#define NCRCMD_MSGOK 0x12 /* Message Accepted */
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#define NCRCMD_TRPAD 0x18 /* Transfer Pad */
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#define NCRCMD_SETATN 0x1a /* Set ATN */
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#define NCRCMD_RSTATN 0x1b /* Reset ATN */
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#define NCR_STAT 0x04 /* RO - Status */
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#define NCRSTAT_INT 0x80 /* Interrupt */
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#define NCRSTAT_GE 0x40 /* Gross Error */
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#define NCRSTAT_PE 0x20 /* Parity Error */
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#define NCRSTAT_TC 0x10 /* Terminal Count */
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#define NCRSTAT_VGC 0x08 /* Valid Group Code */
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#define NCRSTAT_PHASE 0x07 /* Phase bits */
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#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define NCR_BUSID_HMEXC32 0x40 /* HME xfer counter is 32bit */
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#define NCR_BUSID_HMEENCID 0x10 /* HME encode reselection ID */
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#define NCR_INTR 0x05 /* RO - Interrupt */
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#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
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#define NCRINTR_ILL 0x40 /* Illegal Command */
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#define NCRINTR_DIS 0x20 /* Disconnect */
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#define NCRINTR_BS 0x10 /* Bus Service */
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#define NCRINTR_FC 0x08 /* Function Complete */
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#define NCRINTR_RESEL 0x04 /* Reselected */
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#define NCRINTR_SELATN 0x02 /* Select with ATN */
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#define NCRINTR_SEL 0x01 /* Selected */
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#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define NCR_STEP 0x06 /* RO - Sequence Step */
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#define NCRSTEP_MASK 0x07 /* the last 3 bits */
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#define NCRSTEP_DONE 0x04 /* command went out */
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#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
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/* Default 5 (53C9X) */
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#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
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#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
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#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
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#define NCR_SYNCOFF 0x07 /* WO - Synch Offset */
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/* 0 = ASYNC */
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/* 1 - 15 = SYNC bytes */
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#define NCR_CFG1 0x08 /* RW - Configuration #1 */
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#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
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#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
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#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
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#define NCRCFG1_PARENB 0x10 /* Enable Parity Check */
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#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
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#define NCRCFG1_BUSID 0x07 /* Bus ID */
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#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
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/* 0 = 35.01 - 40MHz */
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/* NEVER SET TO 1 */
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/* 2 = 10MHz */
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/* 3 = 10.01 - 15MHz */
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/* 4 = 15.01 - 20MHz */
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/* 5 = 20.01 - 25MHz */
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/* 6 = 25.01 - 30MHz */
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/* 7 = 30.01 - 35MHz */
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#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define NCR_CFG2 0x0b /* RW - Configuration #2 */
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#define NCRCFG2_RSVD 0xa0 /* reserved */
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#define NCRCFG2_FE 0x40 /* Features Enable */
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#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
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#define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */
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#define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */
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#define NCRCFG2_RPE 0x02 /* Register Parity Error */
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#define NCRCFG2_DPE 0x01 /* DMA Parity Error */
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#define NCRCFG2_HMEFE 0x10 /* HME feature enable */
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#define NCRCFG2_HME32 0x80 /* HME 32 extended */
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/* Config #3 only on 53C9X */
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#define NCR_CFG3 0x0c /* RW - Configuration #3 */
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#define NCRCFG3_RSVD 0xe0 /* reserved */
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#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
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#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
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#define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */
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#define NCRCFG3_FSCSI 0x02 /* Fast SCSI */
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#define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */
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/*
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* For some unknown reason, the ESP406/FAS408 looks like every
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* other ncr53c9x, except for configuration #3 register. At any
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* rate, if you're dealing with these chips, you need to use these
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* defines instead.
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*/
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/* Config #3 different on ESP406/FAS408 */
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#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
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#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
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#define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */
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#define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */
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#define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */
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#define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */
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#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
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/* Config #3 also different on NCR53CF9x/FAS100A/FAS216/FAS236 */
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#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
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#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
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#define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */
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#define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */
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#define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */
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#define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */
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#define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */
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/* Config #3 on FAS366 */
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#define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */
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#define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */
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#define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */
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#define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */
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#define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */
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#define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */
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#define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */
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#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
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/* Config #4 only on ESP406/FAS408 */
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#define NCR_CFG4 0x0d /* RW - Configuration #4 */
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#define NCRCFG4_CRS1 0x80 /* Select register set #1 */
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#define NCRCFG4_RSVD 0x7b /* reserved */
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#define NCRCFG4_ACTNEG 0x04 /* Active negation */
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/*
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The following registers are only on the ESP406/FAS408. The
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documentation refers to them as "Control Register Set #1".
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These are the registers that are visible when bit 7 of
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register 0x0d is set. This bit is common to both register sets.
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*/
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#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
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#define NCRJMP_RSVD 0xc0 /* reserved */
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#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
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#define NCRJMP_J4 0x10 /* Jumper #4 */
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#define NCRJMP_J3 0x08 /* Jumper #3 */
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#define NCRJMP_J2 0x04 /* Jumper #2 */
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#define NCRJMP_J1 0x02 /* Jumper #1 */
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#define NCRJMP_J0 0x01 /* Jumper #0 */
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#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
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#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
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#define NCRPSTAT_PERR 0x80 /* PIO Error */
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#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
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#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
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#define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */
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#define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */
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#define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */
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#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
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#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
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#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
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#define NCRPIOI_RSVD 0xe0 /* reserved */
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#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
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#define NCRPIOI_13 0x08 /* IRQ When 1/3 */
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#define NCRPIOI_23 0x04 /* IRQ When 2/3 */
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#define NCRPIOI_FULL 0x02 /* IRQ When Full */
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#define NCRPIOI_FINV 0x01 /* Flag Invert */
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#define NCR_CFG5 0x0d /* RW - Configuration #5 */
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#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
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#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
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#define NCRCFG5_AADDR 0x20 /* Auto Address */
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#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
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#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
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#define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */
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#define NCRCFG5_INTP 0x02 /* INT Polarity */
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#define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */
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#define NCR_SIGNTR 0x0e /* RO - Signature */
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/* Am53c974 Config #3 */
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#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
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#define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */
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#define NCRAMDCFG3_FSCSI 0x10 /* Fast SCSI */
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#define NCRAMDCFG3_FCLK 0x08 /* Fast Clock (40MHz) */
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#define NCRAMDCFG3_RSVD 0x07 /* Reserved */
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/* Am53c974 Config #4 */
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#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
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#define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */
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#define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */
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#define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */
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#define NCRAMDCFG4_GE35NS 0x40 /* Signal window 35ns */
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#define NCRAMDCFG4_GE0NS 0xc0 /* Signal window 0ns */
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#define NCRAMDCFG4_PWD 0x20 /* Reduced power feature */
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#define NCRAMDCFG4_RSVD 0x13 /* Reserved */
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#define NCRAMDCFG4_RAE 0x08 /* Active neg. REQ/ACK */
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#define NCRAMDCFG4_RADE 0x04 /* Active neg. REQ/ACK/DAT */
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/*
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* FAS366
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*/
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#define NCR_RCL NCR_TCH /* Recommand counter low */
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#define NCR_RCH 0xf /* Recommand counter high */
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#define NCR_UID NCR_RCL /* fas366 part-uniq id */
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/* status register #2 definitions (read only) */
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#define NCR_STAT2 NCR_CCF
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#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
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#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
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#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
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#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
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#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
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#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
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#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
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#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
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