ff17a6773e
On the original i386, %dr[4-5] were unimplemented but not very clearly reserved, so debuggers read them to print them. i386 was still doing this. On the original athlon64, %dr[4-5] are documented as reserved but are aliased to %dr[6-7] unless CR4_DE is set, when accessing them traps. On 2 of my systems, accessing %dr[4-5] trapped sometimes. On my Haswell system, the apparent randomness was because the boot CPU starts with CR4_DE set while all other CPUs start with CR4_DE clear. FreeBSD doesn't support the data breakpoints enabled by CR4_DE and it never changes this flag, so the flag remains different across CPUs and the behaviour seemed inconsistent except while booting when the CPU doesn't change. The invalid accesses broke: - read access for printing the registers in ddb "show watches" on CPUs with CR4_DE set - read accesses in fill_dbregs() on CPUs with CR4_DE set. This didn't implement panic(3) since the user case always skipped %dr[4-5]. - write accesses in set_dbregs(). This also didn't affect userland. When it didn't trap, the aliasing made it fragile. Don't print the dummy (zero) values of %dr[4-5] in "show watches" for i386 or amd64. Fix style bugs near this printing. amd64 also has space in the dbregs struct for the reserved %dr[8-15] and already didn't print the dummy values for these, and never accessed any of the 10 reserved debug registers. Remove cpufuncs for making the invalid accesses. Even amd64 had these.
772 lines
14 KiB
C
772 lines
14 KiB
C
/*-
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Functions to provide access to special i386 instructions.
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* This in included in sys/systm.h, and that file should be
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* used in preference to this.
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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struct region_descriptor;
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#define readb(va) (*(volatile uint8_t *) (va))
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#define readw(va) (*(volatile uint16_t *) (va))
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#define readl(va) (*(volatile uint32_t *) (va))
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#define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
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#define writew(va, d) (*(volatile uint16_t *) (va) = (d))
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#define writel(va, d) (*(volatile uint32_t *) (va) = (d))
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#if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
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static __inline void
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breakpoint(void)
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{
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__asm __volatile("int $3");
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}
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static __inline u_int
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bsfl(u_int mask)
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{
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u_int result;
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__asm("bsfl %1,%0" : "=r" (result) : "rm" (mask) : "cc");
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return (result);
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}
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static __inline u_int
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bsrl(u_int mask)
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{
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u_int result;
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__asm("bsrl %1,%0" : "=r" (result) : "rm" (mask) : "cc");
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return (result);
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}
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static __inline void
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clflush(u_long addr)
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{
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__asm __volatile("clflush %0" : : "m" (*(char *)addr));
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}
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static __inline void
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clflushopt(u_long addr)
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{
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__asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
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}
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static __inline void
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clts(void)
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{
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__asm __volatile("clts");
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}
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static __inline void
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disable_intr(void)
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{
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__asm __volatile("cli" : : : "memory");
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}
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static __inline void
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do_cpuid(u_int ax, u_int *p)
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{
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__asm __volatile("cpuid"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax));
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}
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static __inline void
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cpuid_count(u_int ax, u_int cx, u_int *p)
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{
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__asm __volatile("cpuid"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax), "c" (cx));
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}
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static __inline void
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enable_intr(void)
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{
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__asm __volatile("sti");
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}
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static __inline void
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cpu_monitor(const void *addr, u_long extensions, u_int hints)
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{
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__asm __volatile("monitor"
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: : "a" (addr), "c" (extensions), "d" (hints));
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}
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static __inline void
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cpu_mwait(u_long extensions, u_int hints)
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{
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__asm __volatile("mwait" : : "a" (hints), "c" (extensions));
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}
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static __inline void
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lfence(void)
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{
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__asm __volatile("lfence" : : : "memory");
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}
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static __inline void
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mfence(void)
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{
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__asm __volatile("mfence" : : : "memory");
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}
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static __inline void
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sfence(void)
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{
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__asm __volatile("sfence" : : : "memory");
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}
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#ifdef _KERNEL
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#define HAVE_INLINE_FFS
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static __inline int
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ffs(int mask)
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{
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/*
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* Note that gcc-2's builtin ffs would be used if we didn't declare
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* this inline or turn off the builtin. The builtin is faster but
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* broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
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* versions.
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*/
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return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
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}
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#define HAVE_INLINE_FFSL
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static __inline int
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ffsl(long mask)
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{
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return (ffs((int)mask));
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}
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#define HAVE_INLINE_FLS
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static __inline int
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fls(int mask)
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{
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return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
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}
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#define HAVE_INLINE_FLSL
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static __inline int
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flsl(long mask)
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{
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return (fls((int)mask));
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}
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#endif /* _KERNEL */
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static __inline void
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halt(void)
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{
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__asm __volatile("hlt");
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}
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static __inline u_char
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inb(u_int port)
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{
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u_char data;
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__asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
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return (data);
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}
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static __inline u_int
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inl(u_int port)
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{
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u_int data;
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__asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
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return (data);
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}
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static __inline void
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insb(u_int port, void *addr, size_t count)
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{
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__asm __volatile("cld; rep; insb"
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: "+D" (addr), "+c" (count)
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: "d" (port)
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: "memory");
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}
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static __inline void
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insw(u_int port, void *addr, size_t count)
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{
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__asm __volatile("cld; rep; insw"
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: "+D" (addr), "+c" (count)
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: "d" (port)
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: "memory");
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}
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static __inline void
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insl(u_int port, void *addr, size_t count)
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{
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__asm __volatile("cld; rep; insl"
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: "+D" (addr), "+c" (count)
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: "d" (port)
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: "memory");
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}
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static __inline void
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invd(void)
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{
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__asm __volatile("invd");
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}
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static __inline u_short
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inw(u_int port)
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{
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u_short data;
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__asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
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return (data);
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}
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static __inline void
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outb(u_int port, u_char data)
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{
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__asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
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}
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static __inline void
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outl(u_int port, u_int data)
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{
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__asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
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}
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static __inline void
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outsb(u_int port, const void *addr, size_t count)
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{
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__asm __volatile("cld; rep; outsb"
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: "+S" (addr), "+c" (count)
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: "d" (port));
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}
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static __inline void
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outsw(u_int port, const void *addr, size_t count)
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{
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__asm __volatile("cld; rep; outsw"
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: "+S" (addr), "+c" (count)
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: "d" (port));
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}
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static __inline void
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outsl(u_int port, const void *addr, size_t count)
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{
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__asm __volatile("cld; rep; outsl"
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: "+S" (addr), "+c" (count)
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: "d" (port));
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}
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static __inline void
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outw(u_int port, u_short data)
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{
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__asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
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}
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static __inline void
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ia32_pause(void)
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{
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__asm __volatile("pause");
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}
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static __inline u_int
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read_eflags(void)
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{
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u_int ef;
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__asm __volatile("pushfl; popl %0" : "=r" (ef));
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return (ef);
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}
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static __inline uint64_t
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rdmsr(u_int msr)
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{
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uint64_t rv;
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__asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
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return (rv);
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}
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static __inline uint32_t
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rdmsr32(u_int msr)
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{
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uint32_t low;
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__asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "edx");
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return (low);
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}
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static __inline uint64_t
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rdpmc(u_int pmc)
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{
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uint64_t rv;
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__asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc));
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return (rv);
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}
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static __inline uint64_t
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rdtsc(void)
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{
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uint64_t rv;
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__asm __volatile("rdtsc" : "=A" (rv));
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return (rv);
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}
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static __inline uint32_t
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rdtsc32(void)
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{
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uint32_t rv;
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__asm __volatile("rdtsc" : "=a" (rv) : : "edx");
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return (rv);
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}
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static __inline void
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wbinvd(void)
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{
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__asm __volatile("wbinvd");
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}
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static __inline void
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write_eflags(u_int ef)
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{
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__asm __volatile("pushl %0; popfl" : : "r" (ef));
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}
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static __inline void
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wrmsr(u_int msr, uint64_t newval)
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{
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__asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
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}
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static __inline void
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load_cr0(u_int data)
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{
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__asm __volatile("movl %0,%%cr0" : : "r" (data));
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}
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static __inline u_int
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rcr0(void)
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{
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u_int data;
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__asm __volatile("movl %%cr0,%0" : "=r" (data));
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return (data);
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}
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static __inline u_int
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rcr2(void)
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{
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u_int data;
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__asm __volatile("movl %%cr2,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_cr3(u_int data)
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{
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__asm __volatile("movl %0,%%cr3" : : "r" (data) : "memory");
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}
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static __inline u_int
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rcr3(void)
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{
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u_int data;
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__asm __volatile("movl %%cr3,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_cr4(u_int data)
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{
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__asm __volatile("movl %0,%%cr4" : : "r" (data));
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}
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static __inline u_int
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rcr4(void)
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{
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u_int data;
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__asm __volatile("movl %%cr4,%0" : "=r" (data));
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return (data);
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}
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static __inline uint64_t
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rxcr(u_int reg)
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{
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u_int low, high;
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__asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
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return (low | ((uint64_t)high << 32));
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}
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static __inline void
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load_xcr(u_int reg, uint64_t val)
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{
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u_int low, high;
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low = val;
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high = val >> 32;
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__asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
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}
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/*
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* Global TLB flush (except for thise for pages marked PG_G)
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*/
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static __inline void
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invltlb(void)
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{
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load_cr3(rcr3());
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}
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/*
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* TLB flush for an individual page (even if it has PG_G).
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* Only works on 486+ CPUs (i386 does not have PG_G).
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*/
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static __inline void
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invlpg(u_int addr)
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{
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__asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
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}
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static __inline u_short
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rfs(void)
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{
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u_short sel;
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__asm __volatile("movw %%fs,%0" : "=rm" (sel));
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return (sel);
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}
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static __inline uint64_t
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rgdt(void)
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{
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uint64_t gdtr;
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__asm __volatile("sgdt %0" : "=m" (gdtr));
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return (gdtr);
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}
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static __inline u_short
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rgs(void)
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{
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u_short sel;
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__asm __volatile("movw %%gs,%0" : "=rm" (sel));
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return (sel);
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}
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static __inline uint64_t
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ridt(void)
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{
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uint64_t idtr;
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__asm __volatile("sidt %0" : "=m" (idtr));
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return (idtr);
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}
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static __inline u_short
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rldt(void)
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{
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u_short ldtr;
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__asm __volatile("sldt %0" : "=g" (ldtr));
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return (ldtr);
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}
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static __inline u_short
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rss(void)
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{
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u_short sel;
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__asm __volatile("movw %%ss,%0" : "=rm" (sel));
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return (sel);
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}
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static __inline u_short
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rtr(void)
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{
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u_short tr;
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__asm __volatile("str %0" : "=g" (tr));
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return (tr);
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}
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static __inline void
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load_fs(u_short sel)
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{
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__asm __volatile("movw %0,%%fs" : : "rm" (sel));
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}
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static __inline void
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load_gs(u_short sel)
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{
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__asm __volatile("movw %0,%%gs" : : "rm" (sel));
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}
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static __inline void
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lidt(struct region_descriptor *addr)
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|
{
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__asm __volatile("lidt (%0)" : : "r" (addr));
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}
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static __inline void
|
|
lldt(u_short sel)
|
|
{
|
|
__asm __volatile("lldt %0" : : "r" (sel));
|
|
}
|
|
|
|
static __inline void
|
|
ltr(u_short sel)
|
|
{
|
|
__asm __volatile("ltr %0" : : "r" (sel));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr0(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr0,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr0(u_int dr0)
|
|
{
|
|
__asm __volatile("movl %0,%%dr0" : : "r" (dr0));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr1(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr1,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr1(u_int dr1)
|
|
{
|
|
__asm __volatile("movl %0,%%dr1" : : "r" (dr1));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr2(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr2,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr2(u_int dr2)
|
|
{
|
|
__asm __volatile("movl %0,%%dr2" : : "r" (dr2));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr3(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr3,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr3(u_int dr3)
|
|
{
|
|
__asm __volatile("movl %0,%%dr3" : : "r" (dr3));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr6(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr6,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr6(u_int dr6)
|
|
{
|
|
__asm __volatile("movl %0,%%dr6" : : "r" (dr6));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr7(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr7,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr7(u_int dr7)
|
|
{
|
|
__asm __volatile("movl %0,%%dr7" : : "r" (dr7));
|
|
}
|
|
|
|
static __inline u_char
|
|
read_cyrix_reg(u_char reg)
|
|
{
|
|
outb(0x22, reg);
|
|
return inb(0x23);
|
|
}
|
|
|
|
static __inline void
|
|
write_cyrix_reg(u_char reg, u_char data)
|
|
{
|
|
outb(0x22, reg);
|
|
outb(0x23, data);
|
|
}
|
|
|
|
static __inline register_t
|
|
intr_disable(void)
|
|
{
|
|
register_t eflags;
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
return (eflags);
|
|
}
|
|
|
|
static __inline void
|
|
intr_restore(register_t eflags)
|
|
{
|
|
write_eflags(eflags);
|
|
}
|
|
|
|
#else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
|
|
|
|
int breakpoint(void);
|
|
u_int bsfl(u_int mask);
|
|
u_int bsrl(u_int mask);
|
|
void clflush(u_long addr);
|
|
void clts(void);
|
|
void cpuid_count(u_int ax, u_int cx, u_int *p);
|
|
void disable_intr(void);
|
|
void do_cpuid(u_int ax, u_int *p);
|
|
void enable_intr(void);
|
|
void halt(void);
|
|
void ia32_pause(void);
|
|
u_char inb(u_int port);
|
|
u_int inl(u_int port);
|
|
void insb(u_int port, void *addr, size_t count);
|
|
void insl(u_int port, void *addr, size_t count);
|
|
void insw(u_int port, void *addr, size_t count);
|
|
register_t intr_disable(void);
|
|
void intr_restore(register_t ef);
|
|
void invd(void);
|
|
void invlpg(u_int addr);
|
|
void invltlb(void);
|
|
u_short inw(u_int port);
|
|
void lidt(struct region_descriptor *addr);
|
|
void lldt(u_short sel);
|
|
void load_cr0(u_int cr0);
|
|
void load_cr3(u_int cr3);
|
|
void load_cr4(u_int cr4);
|
|
void load_dr0(u_int dr0);
|
|
void load_dr1(u_int dr1);
|
|
void load_dr2(u_int dr2);
|
|
void load_dr3(u_int dr3);
|
|
void load_dr6(u_int dr6);
|
|
void load_dr7(u_int dr7);
|
|
void load_fs(u_short sel);
|
|
void load_gs(u_short sel);
|
|
void ltr(u_short sel);
|
|
void outb(u_int port, u_char data);
|
|
void outl(u_int port, u_int data);
|
|
void outsb(u_int port, const void *addr, size_t count);
|
|
void outsl(u_int port, const void *addr, size_t count);
|
|
void outsw(u_int port, const void *addr, size_t count);
|
|
void outw(u_int port, u_short data);
|
|
u_int rcr0(void);
|
|
u_int rcr2(void);
|
|
u_int rcr3(void);
|
|
u_int rcr4(void);
|
|
uint64_t rdmsr(u_int msr);
|
|
uint64_t rdpmc(u_int pmc);
|
|
u_int rdr0(void);
|
|
u_int rdr1(void);
|
|
u_int rdr2(void);
|
|
u_int rdr3(void);
|
|
u_int rdr6(void);
|
|
u_int rdr7(void);
|
|
uint64_t rdtsc(void);
|
|
u_char read_cyrix_reg(u_char reg);
|
|
u_int read_eflags(void);
|
|
u_int rfs(void);
|
|
uint64_t rgdt(void);
|
|
u_int rgs(void);
|
|
uint64_t ridt(void);
|
|
u_short rldt(void);
|
|
u_short rtr(void);
|
|
void wbinvd(void);
|
|
void write_cyrix_reg(u_char reg, u_char data);
|
|
void write_eflags(u_int ef);
|
|
void wrmsr(u_int msr, uint64_t newval);
|
|
|
|
#endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
|
|
|
|
void reset_dbregs(void);
|
|
|
|
#ifdef _KERNEL
|
|
int rdmsr_safe(u_int msr, uint64_t *val);
|
|
int wrmsr_safe(u_int msr, uint64_t newval);
|
|
#endif
|
|
|
|
#endif /* !_MACHINE_CPUFUNC_H_ */
|