3624354c54
- First off, device drivers really do need to know if they are allocating
MSI or MSI-X messages. MSI requires allocating powerof2() messages for
example where MSI-X does not. To address this, split out the MSI-X
support from pci_msi_count() and pci_alloc_msi() into new driver-visible
functions pci_msix_count() and pci_alloc_msix(). As a result,
pci_msi_count() now just returns a count of the max supported MSI
messages for the device, and pci_alloc_msi() only tries to allocate MSI
messages. To get a count of the max supported MSI-X messages, use
pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix().
pci_release_msi() still handles both MSI and MSI-X messages, however.
As a result of this change, drivers using the existing API will only
use MSI messages and will no longer try to use MSI-X messages.
- Because MSI-X allows for each message to have its own data and address
values (and thus does not require all of the messages to have their
MD vectors allocated as a group), some devices allow for "sparse" use
of MSI-X message slots. For example, if a device supports 8 messages
but the OS is only able to allocate 2 messages, the device may make the
best use of 2 IRQs if it enables the messages at slots 1 and 4 rather
than default of using the first N slots (or indicies) at 1 and 2. To
support this, add a new pci_remap_msix() function that a driver may call
after a successful pci_alloc_msix() (but before allocating any of the
SYS_RES_IRQ resources) to allow the allocated IRQ resources to be
assigned to different message indices. For example, from the earlier
example, after pci_alloc_msix() returned a value of 2, the driver would
call pci_remap_msix() passing in array of integers { 1, 4 } as the
new message indices to use. The rid's for the SYS_RES_IRQ resources
will always match the message indices. Thus, after the call to
pci_remap_msix() the driver would be able to access the first message
in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at
SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based
rather than 0-based so that they will always correspond to the rid
values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt).
To support this API, a new PCIB_REMAP_MSIX() method was added to the
pcib interface to change the message index for a single IRQ.
Tested by: scottl
691 lines
19 KiB
C
691 lines
19 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <isa/isavar.h>
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#ifdef CPU_ELAN
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#include <machine/md_var.h>
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#endif
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#include <machine/legacyvar.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/resource.h>
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#include "pcib_if.h"
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static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
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int pin);
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int
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legacy_pcib_maxslots(device_t dev)
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{
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return 31;
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}
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/* read configuration space register */
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u_int32_t
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legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
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int reg, int bytes)
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{
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return(pci_cfgregread(bus, slot, func, reg, bytes));
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}
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/* write configuration space register */
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void
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legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
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int reg, u_int32_t data, int bytes)
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{
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pci_cfgregwrite(bus, slot, func, reg, data, bytes);
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}
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/* Pass MSI alloc requests up to the nexus. */
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static int
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legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
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int *irqs)
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{
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device_t bus;
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bus = device_get_parent(pcib);
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return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
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irqs));
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}
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static int
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legacy_pcib_alloc_msix(device_t pcib, device_t dev, int index, int *irq)
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{
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device_t bus;
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bus = device_get_parent(pcib);
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return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, index, irq));
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}
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static const char *
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legacy_pcib_is_host_bridge(int bus, int slot, int func,
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uint32_t id, uint8_t class, uint8_t subclass,
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uint8_t *busnum)
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{
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const char *s = NULL;
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static uint8_t pxb[4]; /* hack for 450nx */
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*busnum = 0;
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switch (id) {
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case 0x12258086:
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s = "Intel 824?? host to PCI bridge";
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/* XXX This is a guess */
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/* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
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*busnum = bus;
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break;
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case 0x71208086:
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s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
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break;
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case 0x71228086:
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s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
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break;
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case 0x71248086:
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s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
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break;
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case 0x11308086:
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s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
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break;
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case 0x71808086:
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s = "Intel 82443LX (440 LX) host to PCI bridge";
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break;
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case 0x71908086:
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s = "Intel 82443BX (440 BX) host to PCI bridge";
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break;
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case 0x71928086:
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s = "Intel 82443BX host to PCI bridge (AGP disabled)";
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break;
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case 0x71948086:
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s = "Intel 82443MX host to PCI bridge";
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break;
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case 0x71a08086:
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s = "Intel 82443GX host to PCI bridge";
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break;
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case 0x71a18086:
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s = "Intel 82443GX host to AGP bridge";
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break;
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case 0x71a28086:
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s = "Intel 82443GX host to PCI bridge (AGP disabled)";
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break;
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case 0x84c48086:
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s = "Intel 82454KX/GX (Orion) host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
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break;
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case 0x84ca8086:
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/*
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* For the 450nx chipset, there is a whole bundle of
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* things pretending to be host bridges. The MIOC will
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* be seen first and isn't really a pci bridge (the
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* actual busses are attached to the PXB's). We need to
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* read the registers of the MIOC to figure out the
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* bus numbers for the PXB channels.
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*
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* Since the MIOC doesn't have a pci bus attached, we
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* pretend it wasn't there.
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*/
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pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
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0xd0, 1); /* BUSNO[0] */
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pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
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0xd1, 1) + 1; /* SUBA[0]+1 */
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pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
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0xd3, 1); /* BUSNO[1] */
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pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
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0xd4, 1) + 1; /* SUBA[1]+1 */
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return NULL;
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case 0x84cb8086:
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switch (slot) {
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case 0x12:
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s = "Intel 82454NX PXB#0, Bus#A";
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*busnum = pxb[0];
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break;
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case 0x13:
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s = "Intel 82454NX PXB#0, Bus#B";
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*busnum = pxb[1];
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break;
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case 0x14:
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s = "Intel 82454NX PXB#1, Bus#A";
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*busnum = pxb[2];
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break;
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case 0x15:
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s = "Intel 82454NX PXB#1, Bus#B";
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*busnum = pxb[3];
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break;
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}
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break;
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/* AMD -- vendor 0x1022 */
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case 0x30001022:
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s = "AMD Elan SC520 host to PCI bridge";
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#ifdef CPU_ELAN
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init_AMD_Elan_sc520();
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#else
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printf(
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"*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
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#endif
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break;
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case 0x70061022:
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s = "AMD-751 host to PCI bridge";
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break;
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case 0x700e1022:
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s = "AMD-761 host to PCI bridge";
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break;
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/* SiS -- vendor 0x1039 */
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case 0x04961039:
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s = "SiS 85c496";
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break;
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case 0x04061039:
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s = "SiS 85c501";
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break;
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case 0x06011039:
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s = "SiS 85c601";
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break;
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case 0x55911039:
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s = "SiS 5591 host to PCI bridge";
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break;
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case 0x00011039:
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s = "SiS 5591 host to AGP bridge";
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break;
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/* VLSI -- vendor 0x1004 */
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case 0x00051004:
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s = "VLSI 82C592 Host to PCI bridge";
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break;
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/* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
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/* totally. Please let me know if anything wrong. -F */
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/* XXX need info on the MVP3 -- any takers? */
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case 0x05981106:
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s = "VIA 82C598MVP (Apollo MVP3) host bridge";
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break;
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/* AcerLabs -- vendor 0x10b9 */
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/* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
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/* id is '10b9" but the register always shows "10b9". -Foxfair */
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case 0x154110b9:
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s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
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break;
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/* OPTi -- vendor 0x1045 */
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case 0xc7011045:
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s = "OPTi 82C700 host to PCI bridge";
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break;
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case 0xc8221045:
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s = "OPTi 82C822 host to PCI Bridge";
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break;
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/* ServerWorks -- vendor 0x1166 */
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case 0x00051166:
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s = "ServerWorks NB6536 2.0HE host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00061166:
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/* FALLTHROUGH */
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case 0x00081166:
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/* FALLTHROUGH */
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case 0x02011166:
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/* FALLTHROUGH */
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case 0x010f1014: /* IBM re-badged ServerWorks chipset */
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s = "ServerWorks host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00091166:
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s = "ServerWorks NB6635 3.0LE host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00101166:
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s = "ServerWorks CIOB30 host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00111166:
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/* FALLTHROUGH */
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case 0x03021014: /* IBM re-badged ServerWorks chipset */
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s = "ServerWorks CMIC-HE host to PCI-X bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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/* XXX unknown chipset, but working */
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case 0x00171166:
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/* FALLTHROUGH */
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case 0x01011166:
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s = "ServerWorks host to PCI bridge(unknown chipset)";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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/* Compaq/HP -- vendor 0x0e11 */
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case 0x60100e11:
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s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
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break;
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/* Integrated Micro Solutions -- vendor 0x10e0 */
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case 0x884910e0:
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s = "Integrated Micro Solutions VL Bridge";
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break;
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default:
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if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
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s = "Host to PCI bridge";
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break;
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}
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return s;
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}
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/*
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* Scan the first pci bus for host-pci bridges and add pcib instances
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* to the nexus for each bridge.
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*/
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static void
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legacy_pcib_identify(driver_t *driver, device_t parent)
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{
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int bus, slot, func;
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u_int8_t hdrtype;
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int found = 0;
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int pcifunchigh;
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int found824xx = 0;
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int found_orion = 0;
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device_t child;
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devclass_t pci_devclass;
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if (pci_cfgregopen() == 0)
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return;
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/*
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* Check to see if we haven't already had a PCI bus added
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* via some other means. If we have, bail since otherwise
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* we're going to end up duplicating it.
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*/
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if ((pci_devclass = devclass_find("pci")) &&
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devclass_get_device(pci_devclass, 0))
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return;
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bus = 0;
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retry:
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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func = 0;
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hdrtype = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_HDRTYPE, 1);
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/*
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* When enumerating bus devices, the standard says that
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* one should check the header type and ignore the slots whose
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* header types that the software doesn't know about. We use
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* this to filter out devices.
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*/
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if ((hdrtype & PCIM_MFDEV) &&
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(!found_orion || hdrtype != 0xff))
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pcifunchigh = PCI_FUNCMAX;
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else
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pcifunchigh = 0;
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for (func = 0; func <= pcifunchigh; func++) {
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/*
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* Read the IDs and class from the device.
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*/
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u_int32_t id;
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u_int8_t class, subclass, busnum;
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const char *s;
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device_t *devs;
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int ndevs, i;
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id = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_DEVVENDOR, 4);
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if (id == -1)
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continue;
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class = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_CLASS, 1);
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subclass = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_SUBCLASS, 1);
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s = legacy_pcib_is_host_bridge(bus, slot, func,
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id, class, subclass,
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&busnum);
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if (s == NULL)
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continue;
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/*
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* Check to see if the physical bus has already
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* been seen. Eg: hybrid 32 and 64 bit host
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* bridges to the same logical bus.
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*/
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if (device_get_children(parent, &devs, &ndevs) == 0) {
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for (i = 0; s != NULL && i < ndevs; i++) {
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if (strcmp(device_get_name(devs[i]),
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"pcib") != 0)
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continue;
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if (legacy_get_pcibus(devs[i]) == busnum)
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s = NULL;
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}
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free(devs, M_TEMP);
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}
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|
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if (s == NULL)
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continue;
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/*
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* Add at priority 100 to make sure we
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* go after any motherboard resources
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*/
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child = BUS_ADD_CHILD(parent, 100,
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"pcib", busnum);
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device_set_desc(child, s);
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legacy_set_pcibus(child, busnum);
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found = 1;
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if (id == 0x12258086)
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found824xx = 1;
|
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if (id == 0x84c48086)
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found_orion = 1;
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}
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}
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if (found824xx && bus == 0) {
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bus++;
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goto retry;
|
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}
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|
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/*
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|
* Make sure we add at least one bridge since some old
|
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* hardware doesn't actually have a host-pci bridge device.
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* Note that pci_cfgregopen() thinks we have PCI devices..
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*/
|
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if (!found) {
|
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if (bootverbose)
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printf(
|
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"legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
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child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
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legacy_set_pcibus(child, 0);
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}
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}
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|
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static int
|
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legacy_pcib_probe(device_t dev)
|
|
{
|
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|
|
if (pci_cfgregopen() == 0)
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|
return ENXIO;
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|
return -100;
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|
}
|
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|
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static int
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legacy_pcib_attach(device_t dev)
|
|
{
|
|
device_t pir;
|
|
int bus;
|
|
|
|
/*
|
|
* Look for a PCI BIOS interrupt routing table as that will be
|
|
* our method of routing interrupts if we have one.
|
|
*/
|
|
bus = pcib_get_bus(dev);
|
|
if (pci_pir_probe(bus, 0)) {
|
|
pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
|
|
if (pir != NULL)
|
|
device_probe_and_attach(pir);
|
|
}
|
|
device_add_child(dev, "pci", bus);
|
|
return bus_generic_attach(dev);
|
|
}
|
|
|
|
int
|
|
legacy_pcib_read_ivar(device_t dev, device_t child, int which,
|
|
uintptr_t *result)
|
|
{
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
*result = legacy_get_pcibus(dev);
|
|
return 0;
|
|
}
|
|
return ENOENT;
|
|
}
|
|
|
|
int
|
|
legacy_pcib_write_ivar(device_t dev, device_t child, int which,
|
|
uintptr_t value)
|
|
{
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
legacy_set_pcibus(dev, value);
|
|
return 0;
|
|
}
|
|
return ENOENT;
|
|
}
|
|
|
|
SYSCTL_DECL(_hw_pci);
|
|
|
|
static unsigned long legacy_host_mem_start = 0x80000000;
|
|
TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
|
|
SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
|
|
&legacy_host_mem_start, 0x80000000,
|
|
"Limit the host bridge memory to being above this address. Must be\n\
|
|
set at boot via a tunable.");
|
|
|
|
struct resource *
|
|
legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
|
u_long start, u_long end, u_long count, u_int flags)
|
|
{
|
|
/*
|
|
* If no memory preference is given, use upper 32MB slot most
|
|
* bioses use for their memory window. Typically other bridges
|
|
* before us get in the way to assert their preferences on memory.
|
|
* Hardcoding like this sucks, so a more MD/MI way needs to be
|
|
* found to do it. This is typically only used on older laptops
|
|
* that don't have pci busses behind pci bridge, so assuming > 32MB
|
|
* is liekly OK.
|
|
*
|
|
* However, this can cause problems for other chipsets, so we make
|
|
* this tunable by hw.pci.host_mem_start.
|
|
*/
|
|
if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
|
|
start = legacy_host_mem_start;
|
|
if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
|
|
start = 0x1000;
|
|
return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
|
|
count, flags));
|
|
}
|
|
|
|
static device_method_t legacy_pcib_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_identify, legacy_pcib_identify),
|
|
DEVMETHOD(device_probe, legacy_pcib_probe),
|
|
DEVMETHOD(device_attach, legacy_pcib_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
|
|
DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
|
|
DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
|
|
DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, pcib_release_msi),
|
|
DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
|
|
DEVMETHOD(pcib_remap_msix, pcib_remap_msix),
|
|
DEVMETHOD(pcib_release_msix, pcib_release_msix),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static devclass_t hostb_devclass;
|
|
|
|
DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
|
|
DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
|
|
|
|
|
|
/*
|
|
* Install placeholder to claim the resources owned by the
|
|
* PCI bus interface. This could be used to extract the
|
|
* config space registers in the extreme case where the PnP
|
|
* ID is available and the PCI BIOS isn't, but for now we just
|
|
* eat the PnP ID and do nothing else.
|
|
*
|
|
* XXX we should silence this probe, as it will generally confuse
|
|
* people.
|
|
*/
|
|
static struct isa_pnp_id pcibus_pnp_ids[] = {
|
|
{ 0x030ad041 /* PNP0A03 */, "PCI Bus" },
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
pcibus_pnp_probe(device_t dev)
|
|
{
|
|
int result;
|
|
|
|
if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
|
|
device_quiet(dev);
|
|
return(result);
|
|
}
|
|
|
|
static int
|
|
pcibus_pnp_attach(device_t dev)
|
|
{
|
|
return(0);
|
|
}
|
|
|
|
static device_method_t pcibus_pnp_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, pcibus_pnp_probe),
|
|
DEVMETHOD(device_attach, pcibus_pnp_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static devclass_t pcibus_pnp_devclass;
|
|
|
|
DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
|
|
DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
|
|
|
|
|
|
/*
|
|
* Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
|
|
* that appear in the PCIBIOS Interrupt Routing Table to use the routing
|
|
* table for interrupt routing when possible.
|
|
*/
|
|
static int pcibios_pcib_probe(device_t bus);
|
|
|
|
static device_method_t pcibios_pcib_pci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, pcibios_pcib_probe),
|
|
DEVMETHOD(device_attach, pcib_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, pcib_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, pcib_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, pcib_maxslots),
|
|
DEVMETHOD(pcib_read_config, pcib_read_config),
|
|
DEVMETHOD(pcib_write_config, pcib_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
|
|
DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, pcib_release_msi),
|
|
DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
|
|
DEVMETHOD(pcib_remap_msix, pcib_remap_msix),
|
|
DEVMETHOD(pcib_release_msix, pcib_release_msix),
|
|
|
|
{0, 0}
|
|
};
|
|
|
|
static devclass_t pcib_devclass;
|
|
|
|
DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
|
|
sizeof(struct pcib_softc));
|
|
DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
|
|
|
|
static int
|
|
pcibios_pcib_probe(device_t dev)
|
|
{
|
|
int bus;
|
|
|
|
if ((pci_get_class(dev) != PCIC_BRIDGE) ||
|
|
(pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
|
|
return (ENXIO);
|
|
bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
|
|
if (bus == 0)
|
|
return (ENXIO);
|
|
if (!pci_pir_probe(bus, 1))
|
|
return (ENXIO);
|
|
device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
|
|
return (-2000);
|
|
}
|
|
|
|
static int
|
|
pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
|
|
{
|
|
return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
|
|
pci_get_function(dev), pin));
|
|
}
|