d212022417
o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
345 lines
14 KiB
C
345 lines
14 KiB
C
/* $NetBSD: ehcireg.h,v 1.18 2004/10/22 10:38:17 augustss Exp $ */
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The EHCI 0.96 spec can be found at
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* http://developer.intel.com/technology/usb/download/ehci-r096.pdf
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* and the USB 2.0 spec at
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* http://www.usb.org/developers/data/usb_20.zip
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*/
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#ifndef _DEV_PCI_EHCIREG_H_
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#define _DEV_PCI_EHCIREG_H_
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/*** PCI config registers ***/
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#define PCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_INTERFACE_EHCI 0x20
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#define PCI_USBREV 0x60 /* RO USB protocol revision */
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#define PCI_USBREV_MASK 0xff
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#define PCI_USBREV_PRE_1_0 0x00
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#define PCI_USBREV_1_0 0x10
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#define PCI_USBREV_1_1 0x11
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#define PCI_USBREV_2_0 0x20
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#define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */
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#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
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/* EHCI Extended Capabilities */
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#define EHCI_EC_LEGSUP 0x01
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#define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff)
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#define EHCI_EECP_ID(x) ((x) & 0xff)
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/* Legacy support extended capability */
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#define EHCI_LEGSUP_OS_SEM 0x03 /* OS owned semaphore */
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#define EHCI_LEGSUP_BIOS_SEM 0x02 /* BIOS owned semaphore */
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#define EHCI_LEGSUP_USBLEGCTLSTS 0x04
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/*** EHCI capability registers ***/
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#define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */
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/* reserved 0x01 */
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#define EHCI_HCIVERSION 0x02 /* RO Interface version number */
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#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
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#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
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#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
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#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */
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#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */
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#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
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#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */
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#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */
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#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */
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#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */
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#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */
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#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */
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#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */
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#define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */
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/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */
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#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */
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#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */
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#define EHCI_CMD_ITC_1 0x00010000
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#define EHCI_CMD_ITC_2 0x00020000
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#define EHCI_CMD_ITC_4 0x00040000
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#define EHCI_CMD_ITC_8 0x00080000
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#define EHCI_CMD_ITC_16 0x00100000
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#define EHCI_CMD_ITC_32 0x00200000
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#define EHCI_CMD_ITC_64 0x00400000
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#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */
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#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */
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#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */
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#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */
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#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */
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#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */
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#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */
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#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */
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#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */
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#define EHCI_CMD_RS 0x00000001 /* RW run/stop */
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#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */
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#define EHCI_STS_ASS 0x00008000 /* RO async sched status */
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#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */
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#define EHCI_STS_REC 0x00002000 /* RO reclamation */
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#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */
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#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */
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#define EHCI_STS_HSE 0x00000010 /* RWC host system error */
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#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */
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#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
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#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */
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#define EHCI_STS_INT 0x00000001 /* RWC interrupt */
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#define EHCI_STS_INTRS(x) ((x) & 0x3f)
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#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
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#define EHCI_USBINTR 0x08 /* RW Interrupt register */
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#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */
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#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */
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#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */
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#define EHCI_INTR_PCIE 0x00000004 /* port change ena */
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#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */
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#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */
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#define EHCI_FRINDEX 0x0c /* RW Frame Index register */
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#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */
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#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */
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#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */
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#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */
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#define EHCI_CONF_CF 0x00000001 /* RW configure flag */
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#define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
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#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */
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#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
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#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
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#define EHCI_PS_PTC 0x000f0000 /* RW port test control */
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#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
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#define EHCI_PS_PO 0x00002000 /* RW port owner */
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#define EHCI_PS_PP 0x00001000 /* RW,RO port power */
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#define EHCI_PS_LS 0x00000c00 /* RO line status */
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#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
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#define EHCI_PS_PR 0x00000100 /* RW port reset */
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#define EHCI_PS_SUSP 0x00000080 /* RW suspend */
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#define EHCI_PS_FPR 0x00000040 /* RW force port resume */
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#define EHCI_PS_OCC 0x00000020 /* RWC over current change */
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#define EHCI_PS_OCA 0x00000010 /* RO over current active */
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#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
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#define EHCI_PS_PE 0x00000004 /* RW port enable */
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#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
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#define EHCI_PS_CS 0x00000001 /* RO connect status */
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#define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
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#define EHCI_USBMODE 0x68 /* RW USB Device mode register */
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#define EHCI_UM_CM 0x00000003 /* R/WO Controller Mode */
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#define EHCI_UM_CM_IDLE 0x0 /* Idle */
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#define EHCI_UM_CM_HOST 0x3 /* Host Controller */
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#define EHCI_UM_ES 0x00000004 /* R/WO Endian Select */
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#define EHCI_UM_ES_LE 0x0 /* Little-endian byte alignment */
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#define EHCI_UM_ES_BE 0x4 /* Big-endian byte alignment */
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#define EHCI_UM_SDIS 0x00000010 /* R/WO Stream Disable Mode */
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#define EHCI_PORT_RESET_COMPLETE 2 /* ms */
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#define EHCI_FLALIGN_ALIGN 0x1000
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/* No data structure may cross a page boundary. */
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#define EHCI_PAGE_SIZE 0x1000
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#define EHCI_PAGE(x) ((x) &~ 0xfff)
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#define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
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#if defined(__FreeBSD__)
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#define EHCI_PAGE_MASK(x) ((x) & 0xfff)
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#endif
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typedef u_int32_t ehci_link_t;
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#define EHCI_LINK_TERMINATE 0x00000001
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#define EHCI_LINK_TYPE(x) ((x) & 0x00000006)
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#define EHCI_LINK_ITD 0x0
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#define EHCI_LINK_QH 0x2
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#define EHCI_LINK_SITD 0x4
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#define EHCI_LINK_FSTN 0x6
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#define EHCI_LINK_ADDR(x) ((x) &~ 0x1f)
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typedef u_int32_t ehci_physaddr_t;
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typedef u_int32_t ehci_isoc_trans_t;
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typedef u_int32_t ehci_isoc_bufr_ptr_t;
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/* Isochronous Transfer Descriptor */
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typedef struct {
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ehci_link_t itd_next;
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ehci_isoc_trans_t itd_ctl[8];
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#define EHCI_ITD_GET_STATUS(x) (((x) >> 28) & 0xf)
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#define EHCI_ITD_SET_STATUS(x) (((x) & 0xf) << 28)
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#define EHCI_ITD_ACTIVE 0x80000000
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#define EHCI_ITD_BUF_ERR 0x40000000
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#define EHCI_ITD_BABBLE 0x20000000
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#define EHCI_ITD_ERROR 0x10000000
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#define EHCI_ITD_GET_LEN(x) (((x) >> 16) & 0xfff)
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#define EHCI_ITD_SET_LEN(x) (((x) & 0xfff) << 16)
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#define EHCI_ITD_IOC 0x8000
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#define EHCI_ITD_GET_IOC(x) (((x) >> 15) & 1)
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#define EHCI_ITD_SET_IOC(x) (((x) << 15) & EHCI_ITD_IOC)
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#define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0xf)
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#define EHCI_ITD_SET_PG(x) (((x) & 0xf) << 12)
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#define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xfff)
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#define EHCI_ITD_SET_OFFS(x) (((x) & 0xfff) << 0)
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ehci_isoc_bufr_ptr_t itd_bufr[7];
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#define EHCI_ITD_GET_BPTR(x) ((x) & 0xfffff000)
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#define EHCI_ITD_SET_BPTR(x) ((x) & 0xfffff000)
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#define EHCI_ITD_GET_EP(x) (((x) >> 8) & 0xf)
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#define EHCI_ITD_SET_EP(x) (((x) & 0xf) << 8)
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#define EHCI_ITD_GET_DADDR(x) ((x) & 0x7f)
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#define EHCI_ITD_SET_DADDR(x) ((x) & 0x7f)
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#define EHCI_ITD_GET_DIR(x) (((x) >> 11) & 1)
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#define EHCI_ITD_SET_DIR(x) (((x) & 1) << 11)
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#define EHCI_ITD_GET_MAXPKT(x) ((x) & 0x7ff)
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#define EHCI_ITD_SET_MAXPKT(x) ((x) & 0x7ff)
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#define EHCI_ITD_GET_MULTI(x) ((x) & 0x3)
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#define EHCI_ITD_SET_MULTI(x) ((x) & 0x3)
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} ehci_itd_t;
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#define EHCI_ITD_ALIGN 32
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/* Split Transaction Isochronous Transfer Descriptor */
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typedef struct {
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ehci_link_t sitd_next;
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/* XXX many more */
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} ehci_sitd_t;
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#define EHCI_SITD_ALIGN 32
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/* Queue Element Transfer Descriptor */
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#define EHCI_QTD_NBUFFERS 5
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typedef struct {
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ehci_link_t qtd_next;
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ehci_link_t qtd_altnext;
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u_int32_t qtd_status;
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#define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff)
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#define EHCI_QTD_SET_STATUS(x) ((x) << 0)
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#define EHCI_QTD_ACTIVE 0x80
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#define EHCI_QTD_HALTED 0x40
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#define EHCI_QTD_BUFERR 0x20
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#define EHCI_QTD_BABBLE 0x10
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#define EHCI_QTD_XACTERR 0x08
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#define EHCI_QTD_MISSEDMICRO 0x04
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#define EHCI_QTD_SPLITXSTATE 0x02
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#define EHCI_QTD_PINGSTATE 0x01
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#define EHCI_QTD_STATERRS 0x7c
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#define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3)
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#define EHCI_QTD_SET_PID(x) ((x) << 8)
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#define EHCI_QTD_PID_OUT 0x0
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#define EHCI_QTD_PID_IN 0x1
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#define EHCI_QTD_PID_SETUP 0x2
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#define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3)
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#define EHCI_QTD_SET_CERR(x) ((x) << 10)
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#define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7)
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#define EHCI_QTD_SET_C_PAGE(x) ((x) << 12)
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#define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1)
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#define EHCI_QTD_IOC 0x00008000
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#define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff)
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#define EHCI_QTD_SET_BYTES(x) ((x) << 16)
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#define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1)
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#define EHCI_QTD_SET_TOGGLE(x) ((x) << 31)
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#define EHCI_QTD_TOGGLE_MASK 0x80000000
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ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
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ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
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} ehci_qtd_t;
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#define EHCI_QTD_ALIGN 32
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#define EHCI_QTD_STATUS_BITS \
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"\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING"
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/* Queue Head */
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typedef struct {
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ehci_link_t qh_link;
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u_int32_t qh_endp;
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#define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */
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#define EHCI_QH_SET_ADDR(x) (x)
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#define EHCI_QH_ADDRMASK 0x0000007f
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#define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */
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#define EHCI_QH_INACT 0x00000080
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#define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */
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#define EHCI_QH_SET_ENDPT(x) ((x) << 8)
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#define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */
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#define EHCI_QH_SET_EPS(x) ((x) << 12)
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#define EHCI_QH_SPEED_FULL 0x0
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#define EHCI_QH_SPEED_LOW 0x1
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#define EHCI_QH_SPEED_HIGH 0x2
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#define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */
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#define EHCI_QH_DTC 0x00004000
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#define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */
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#define EHCI_QH_HRECL 0x00008000
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#define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */
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#define EHCI_QH_SET_MPL(x) ((x) << 16)
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#define EHCI_QH_MPLMASK 0x07ff0000
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#define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */
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#define EHCI_QH_CTL 0x08000000
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#define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */
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#define EHCI_QH_SET_NRL(x) ((x) << 28)
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u_int32_t qh_endphub;
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#define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */
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#define EHCI_QH_SET_SMASK(x) ((x) << 0)
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#define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */
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#define EHCI_QH_SET_CMASK(x) ((x) << 8)
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#define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */
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#define EHCI_QH_SET_HUBA(x) ((x) << 16)
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#define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */
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#define EHCI_QH_SET_PORT(x) ((x) << 23)
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#define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */
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#define EHCI_QH_SET_MULT(x) ((x) << 30)
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ehci_link_t qh_curqtd;
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ehci_qtd_t qh_qtd;
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} ehci_qh_t;
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#define EHCI_QH_ALIGN 32
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/* Periodic Frame Span Traversal Node */
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typedef struct {
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ehci_link_t fstn_link;
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ehci_link_t fstn_back;
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} ehci_fstn_t;
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#define EHCI_FSTN_ALIGN 32
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#endif /* _DEV_PCI_EHCIREG_H_ */
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