3672ee2e9a
controllers. TX/RX interrupt mitigation is controlled by VGE_TXSUPPTHR and VGE_RXSUPPTHR register. These registers suppress generation of interrupts until the programmed frames counter equals to the registers. VT61xx also supports interrupt hold off timer register. If this interrupt hold off timer is active all interrupts would be disabled until the timer reaches to 0. The timer value is reloaded whenever VGE_ISR register written. The timer resolution is about 20us. Previously vge(4) used single shot timer to reduce Tx completion interrupts. This required VGE_CRS1 register access in Tx start/completion handler to rearm new timeout value and it did not show satisfactory result(more than 50k interrupts under load). Rx interrupts was not moderated at all such that vge(4) used to generate too many interrupts which in turn made polling(4) better approach under high network load. This change activates all interrupt moderation mechanism and initial values were tuned to generate interrupt less than 8k per second. That number of interrupts wouldn't add additional packet latencies compared to polling(4). These interrupt parameters could be changed with sysctl. dev.vge.%d.int_holdoff dev.vge.%d.rx_coal_pkt dev.vge.%d.tx_coal_pkt Interface has be brought down and up again before change take effect. With interrupt moderation there is no more need to loop in interrupt handler. This loop always added one more register access. While I'm here remove dead code which tried to implement subset of interrupt moderation.
246 lines
7.3 KiB
C
246 lines
7.3 KiB
C
/*-
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define VGE_JUMBO_MTU 9000
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#define VGE_TX_DESC_CNT 256
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#define VGE_RX_DESC_CNT 252 /* Must be a multiple of 4!! */
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#define VGE_TX_RING_ALIGN 64
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#define VGE_RX_RING_ALIGN 64
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#define VGE_MAXTXSEGS 6
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#define VGE_RX_BUF_ALIGN sizeof(uint32_t)
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/*
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* VIA Velocity allows 64bit DMA addressing but high 16bits
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* of the DMA address should be the same for Tx/Rx buffers.
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* Because this condition can't be guaranteed vge(4) limit
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* DMA address space to 48bits.
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*/
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#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
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#define VGE_BUF_DMA_MAXADDR BUS_SPACE_MAXADDR
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#else
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#define VGE_BUF_DMA_MAXADDR 0xFFFFFFFFFFFF
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#endif
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#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
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#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
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#define VGE_TX_DESC_INC(x) ((x) = ((x) + 1) % VGE_TX_DESC_CNT)
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#define VGE_TX_DESC_DEC(x) \
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((x) = (((x) + VGE_TX_DESC_CNT - 1) % VGE_TX_DESC_CNT))
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#define VGE_RX_DESC_INC(x) ((x) = ((x) + 1) % VGE_RX_DESC_CNT)
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#define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
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#define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32)
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#define VGE_BUFLEN(y) ((y) & 0x3FFF)
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#define VGE_RXBYTES(x) (((x) & VGE_RDSTS_BUFSIZ) >> 16)
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#define VGE_MIN_FRAMELEN 60
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#define VGE_INT_HOLDOFF_TICK 20
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#define VGE_INT_HOLDOFF_USEC(x) ((x) / VGE_INT_HOLDOFF_TICK)
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#define VGE_INT_HOLDOFF_MIN 0
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#define VGE_INT_HOLDOFF_MAX (255 * VGE_INT_HOLDOFF_TICK)
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#define VGE_INT_HOLDOFF_DEFAULT 150
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#define VGE_RX_COAL_PKT_MIN 1
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#define VGE_RX_COAL_PKT_MAX VGE_RX_DESC_CNT
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#define VGE_RX_COAL_PKT_DEFAULT 64
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#define VGE_TX_COAL_PKT_MIN 1
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#define VGE_TX_COAL_PKT_MAX VGE_TX_DESC_CNT
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#define VGE_TX_COAL_PKT_DEFAULT 128
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struct vge_type {
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uint16_t vge_vid;
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uint16_t vge_did;
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char *vge_name;
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};
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struct vge_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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struct vge_tx_desc *tx_desc;
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struct vge_txdesc *txd_prev;
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};
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struct vge_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct vge_rx_desc *rx_desc;
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struct vge_rxdesc *rxd_prev;
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};
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struct vge_chain_data{
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bus_dma_tag_t vge_ring_tag;
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bus_dma_tag_t vge_buffer_tag;
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bus_dma_tag_t vge_tx_tag;
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struct vge_txdesc vge_txdesc[VGE_TX_DESC_CNT];
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bus_dma_tag_t vge_rx_tag;
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struct vge_rxdesc vge_rxdesc[VGE_RX_DESC_CNT];
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bus_dma_tag_t vge_tx_ring_tag;
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bus_dmamap_t vge_tx_ring_map;
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bus_dma_tag_t vge_rx_ring_tag;
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bus_dmamap_t vge_rx_ring_map;
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bus_dmamap_t vge_rx_sparemap;
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int vge_tx_prodidx;
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int vge_tx_considx;
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int vge_tx_cnt;
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int vge_rx_prodidx;
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int vge_rx_commit;
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struct mbuf *vge_head;
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struct mbuf *vge_tail;
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};
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#define VGE_CHAIN_RESET(_sc) \
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do { \
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if ((_sc)->vge_cdata.vge_head != NULL) { \
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m_freem((_sc)->vge_cdata.vge_head); \
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(_sc)->vge_cdata.vge_head = NULL; \
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(_sc)->vge_cdata.vge_tail = NULL; \
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} \
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} while (0);
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struct vge_ring_data {
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struct vge_tx_desc *vge_tx_ring;
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bus_addr_t vge_tx_ring_paddr;
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struct vge_rx_desc *vge_rx_ring;
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bus_addr_t vge_rx_ring_paddr;
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};
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struct vge_hw_stats {
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uint32_t rx_frames;
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uint32_t rx_good_frames;
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uint32_t rx_fifo_oflows;
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uint32_t rx_runts;
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uint32_t rx_runts_errs;
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uint32_t rx_pkts_64;
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uint32_t rx_pkts_65_127;
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uint32_t rx_pkts_128_255;
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uint32_t rx_pkts_256_511;
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uint32_t rx_pkts_512_1023;
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uint32_t rx_pkts_1024_1518;
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uint32_t rx_pkts_1519_max;
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uint32_t rx_pkts_1519_max_errs;
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uint32_t rx_jumbos;
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uint32_t rx_crcerrs;
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uint32_t rx_pause_frames;
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uint32_t rx_alignerrs;
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uint32_t rx_nobufs;
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uint32_t rx_symerrs;
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uint32_t rx_lenerrs;
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uint32_t tx_good_frames;
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uint32_t tx_pkts_64;
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uint32_t tx_pkts_65_127;
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uint32_t tx_pkts_128_255;
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uint32_t tx_pkts_256_511;
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uint32_t tx_pkts_512_1023;
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uint32_t tx_pkts_1024_1518;
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uint32_t tx_jumbos;
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uint32_t tx_colls;
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uint32_t tx_pause;
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uint32_t tx_sqeerrs;
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uint32_t tx_latecolls;
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};
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struct vge_softc {
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struct ifnet *vge_ifp; /* interface info */
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device_t vge_dev;
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struct resource *vge_res;
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struct resource *vge_irq;
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void *vge_intrhand;
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device_t vge_miibus;
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uint8_t vge_type;
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int vge_if_flags;
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int vge_phyaddr;
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int vge_flags;
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#define VGE_FLAG_PCIE 0x0001
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#define VGE_FLAG_MSI 0x0002
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#define VGE_FLAG_SUSPENDED 0x4000
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#define VGE_FLAG_LINK 0x8000
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int vge_expcap;
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int vge_camidx;
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int vge_int_holdoff;
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int vge_rx_coal_pkt;
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int vge_tx_coal_pkt;
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struct mtx vge_mtx;
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struct callout vge_watchdog;
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int vge_timer;
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struct vge_chain_data vge_cdata;
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struct vge_ring_data vge_rdata;
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struct vge_hw_stats vge_stats;
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};
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#define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx)
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#define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx)
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#define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_STREAM_4(sc, reg, val) \
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bus_write_stream_4(sc->vge_res, reg, val)
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#define CSR_WRITE_4(sc, reg, val) \
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bus_write_4(sc->vge_res, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_write_2(sc->vge_res, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_write_1(sc->vge_res, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_read_4(sc->vge_res, reg)
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#define CSR_READ_2(sc, reg) \
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bus_read_2(sc->vge_res, reg)
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#define CSR_READ_1(sc, reg) \
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bus_read_1(sc->vge_res, reg)
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#define CSR_SETBIT_1(sc, reg, x) \
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CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
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#define CSR_SETBIT_2(sc, reg, x) \
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CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
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#define CSR_SETBIT_4(sc, reg, x) \
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CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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#define CSR_CLRBIT_1(sc, reg, x) \
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CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
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#define CSR_CLRBIT_2(sc, reg, x) \
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CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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#define CSR_CLRBIT_4(sc, reg, x) \
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CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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#define VGE_RXCHUNK 4
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#define VGE_TIMEOUT 10000
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