03b1e82fd5
in asm files. 2. Temporarily cause subnormal operands in floating point operations to be treated as zeros so that comlpetion of the operation does not need to be emulated. 3. Catch fp_exception_other and correctly skip over the unfinished instruction, but basically ignore them. Emulating the instruction is not yet supported. 4. Zero td_retval[1] as well in syscall(). Submitted by: tmm (2, 3)
106 lines
3.9 KiB
C
106 lines
3.9 KiB
C
/*-
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* Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_FSR_H_
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#define _MACHINE_FSR_H_
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#define FPRS_DL (1 << 0)
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#define FPRS_DU (1 << 1)
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#define FPRS_FEF (1 << 2)
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#define FSR_EXC_BITS 5
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#define FSR_EXC_MASK ((1 << FSR_EXC_BITS) - 1)
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#define FSR_CEXC_SHIFT 0
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#define FSR_CEXC_MASK (FSR_EXC_MASK << FSR_CEXC_SHIFT)
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#define FSR_CEXC(b) ((b) << FSR_CEXC_SHIFT)
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#define FSR_AEXC_SHIFT 5
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#define FSR_AEXC_MASK (FSR_EXC_MASK << FSR_AEXC_SHIFT)
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#define FSR_AEXC(b) ((b) << FSR_AEXC_SHIFT)
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#define FSR_QNE (1 << 13)
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#define FSR_NS (1 << 22)
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#define FSR_TEM_SHIFT 23
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#define FSR_TEM_MASK (FSR_EXC_MASK << FSR_TEM_SHIFT)
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#define FSR_TEM(b) ((b) << FSR_TEM_SHIFT)
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#define FSR_FCC0_SHIFT 10
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#define FSR_FCC0_BITS 2
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#define FSR_FCC0_MASK (((1 << FSR_FCC0_BITS) - 1) << FSR_FCC0_SHIFT)
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#define FSR_FCC0(x) ((x) << FSR_FCC0_SHIFT)
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#define FSR_GET_FCC0(x) (((x) >> FSR_FCC0_SHIFT) & 3)
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#define FSR_FTT_SHIFT 14
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#define FSR_FTT_BITS 3
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#define FSR_FTT_MASK (((1 << FSR_FTT_BITS) - 1) << FSR_FTT_SHIFT)
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#define FSR_FTT(x) ((x) << FSR_FTT_SHIFT)
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#define FSR_GET_FTT(x) (((x) & FSR_FTT_MASK) >> FSR_FTT_SHIFT)
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#define FSR_VER_SHIFT 17
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#define FSR_GET_VER(x) (((x) >> FSR_VER_SHIFT) & 7)
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#define FSR_RD_SHIFT 30
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#define FSR_RD_BITS 2
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#define FSR_RD_MASK (((1 << FSR_RD_BITS) - 1) << FSR_RD_SHIFT)
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#define FSR_RD(x) ((x) << FSR_RD_SHIFT)
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#define FSR_GET_RD(x) (((x) >> FSR_RD_SHIFT) & 3)
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#define FSR_FCC1_SHIFT 32
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#define FSR_FCC1_BITS 2
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#define FSR_FCC1_MASK (((1 << FSR_FCC1_BITS) - 1) << FSR_FCC1_SHIFT)
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#define FSR_FCC1(x) ((x) << FSR_FCC1_SHIFT)
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#define FSR_GET_FCC1(x) (((x) >> FSR_FCC1_SHIFT) & 3)
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#define FSR_FCC2_SHIFT 34
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#define FSR_FCC2_BITS 2
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#define FSR_FCC2_MASK (((1 << FSR_FCC2_BITS) - 1) << FSR_FCC2_SHIFT)
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#define FSR_FCC2(x) ((x) << FSR_FCC2_SHIFT)
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#define FSR_GET_FCC2(x) (((x) >> FSR_FCC2_SHIFT) & 3)
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#define FSR_FCC3_SHIFT 36
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#define FSR_FCC3_BITS 2
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#define FSR_FCC3_MASK (((1 << FSR_FCC3_BITS) - 1) << FSR_FCC3_SHIFT)
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#define FSR_FCC3(x) ((x) << FSR_FCC3_SHIFT)
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#define FSR_GET_FCC3(x) (((x) >> FSR_FCC3_SHIFT) & 3)
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/* CEXC/AEXC/TEM exception values */
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#define FSR_NX (1 << 0)
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#define FSR_DZ (1 << 1)
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#define FSR_UF (1 << 2)
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#define FSR_OF (1 << 3)
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#define FSR_NV (1 << 4)
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/* FTT values. */
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#define FSR_FTT_NONE 0
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#define FSR_FTT_IEEE 1
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#define FSR_FTT_UNFIN 2
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#define FSR_FTT_UNIMP 3
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#define FSR_FTT_SEQERR 4
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#define FSR_FTT_HWERR 5
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#define FSR_FTT_INVREG 6
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/* RD values */
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#define FSR_RD_N 0 /* nearest */
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#define FSR_RD_Z 1 /* zero */
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#define FSR_RD_PINF 2 /* +infinity */
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#define FSR_RD_NINF 3 /* -infinity */
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/* condition codes */
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#define FSR_CC_EQ 0 /* a = b */
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#define FSR_CC_LT 1 /* a < b */
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#define FSR_CC_GT 2 /* a > b */
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#define FSR_CC_UO 3 /* unordered */
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#endif /* !_MACHINE_FSR_H_ */
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