e1529e5239
Scope of this change is somewhat larger than just converting to INTRNG. The reason for this is that INTRNG support required switching from custom to upstream DTS because custom DTS didn't have interrup routing information. This switch caused rewrite of PCI and CLCD drivers and adding SCM module. List of changes in this commit: - Enable INTRNG and switch to versatile-pb.dts - Add SCM driver that controls various peripheral devices like LCD or PCI controller. Previously registers required for power-up and configuring peripherals were part of their respective nodes. Upstream DTS has dedicated node for SCM - Convert PL190 driver to INTRNG - Convert Versatile SIC (secondary interrupt controller) to INTRNG - Refactor CLCD driver to use SCM API to power up and configuration - Refactor PCI driver to use SCM API to enable controller - Refactor PCI driver to use interrupt map provided in DTS for interrupt routing. As a result it fixes broken IRQ routing and it's no longer required to run QEMU with "-global versatile_pci.broken-irq-mapping=1" command-line arguments
545 lines
14 KiB
C
545 lines
14 KiB
C
/*
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* Copyright (c) 2012-2017 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/watchdog.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <arm/versatile/versatile_scm.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#define MEM_CORE 0
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#define MEM_BASE 1
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#define MEM_CONF_BASE 2
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#define MEM_REGIONS 3
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#define PCI_CORE_IMAP0 0x00
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#define PCI_CORE_IMAP1 0x04
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#define PCI_CORE_IMAP2 0x08
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#define PCI_CORE_SELFID 0x0C
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#define PCI_CORE_SMAP0 0x10
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#define PCI_CORE_SMAP1 0x14
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#define PCI_CORE_SMAP2 0x18
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#define VERSATILE_PCI_DEV 0x030010ee
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#define VERSATILE_PCI_CLASS 0x0b400000
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#define PCI_IO_WINDOW 0x44000000
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#define PCI_IO_SIZE 0x0c000000
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#define PCI_NPREFETCH_WINDOW 0x50000000
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#define PCI_NPREFETCH_SIZE 0x10000000
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#define PCI_PREFETCH_WINDOW 0x60000000
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#define PCI_PREFETCH_SIZE 0x10000000
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#define VERSATILE_PCI_IRQ_START 27
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#define VERSATILE_PCI_IRQ_END 30
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#ifdef DEBUG
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#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define dprintf(fmt, args...)
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#endif
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#define versatile_pci_core_read_4(reg) \
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bus_read_4(sc->mem_res[MEM_CORE], (reg))
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#define versatile_pci_core_write_4(reg, val) \
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bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
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#define versatile_pci_read_4(reg) \
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bus_read_4(sc->mem_res[MEM_BASE], (reg))
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#define versatile_pci_write_4(reg, val) \
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bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
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#define versatile_pci_conf_read_4(reg) \
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bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
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#define versatile_pci_conf_write_4(reg, val) \
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bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
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#define versatile_pci_conf_write_2(reg, val) \
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bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
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#define versatile_pci_conf_write_1(reg, val) \
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bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
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struct versatile_pci_softc {
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struct resource* mem_res[MEM_REGIONS];
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struct resource* irq_res;
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void* intr_hl;
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int pcib_slot;
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/* Bus part */
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int busno;
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struct rman io_rman;
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struct rman irq_rman;
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struct rman mem_rman;
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struct mtx mtx;
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struct ofw_bus_iinfo pci_iinfo;
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};
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static struct resource_spec versatile_pci_mem_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ -1, 0, 0 }
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};
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static int
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versatile_pci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "arm,versatile-pci")) {
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device_set_desc(dev, "Versatile PCI controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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versatile_pci_attach(device_t dev)
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{
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struct versatile_pci_softc *sc = device_get_softc(dev);
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int err;
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int slot;
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uint32_t vendordev_id, class_id;
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uint32_t val;
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phandle_t node;
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node = ofw_bus_get_node(dev);
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/* Request memory resources */
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err = bus_alloc_resources(dev, versatile_pci_mem_spec,
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sc->mem_res);
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if (err) {
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device_printf(dev, "Error: could not allocate memory resources\n");
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return (ENXIO);
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}
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/*
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* Setup memory windows
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*/
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versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
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versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
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versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
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/*
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* XXX: this is SDRAM offset >> 28
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* Unused as of QEMU 1.5
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*/
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versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
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versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
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versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
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versatile_scm_reg_write_4(SCM_PCICTL, 1);
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
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class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
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if ((vendordev_id == VERSATILE_PCI_DEV) &&
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(class_id == VERSATILE_PCI_CLASS))
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break;
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}
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if (slot == (PCI_SLOTMAX + 1)) {
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bus_release_resources(dev, versatile_pci_mem_spec,
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sc->mem_res);
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device_printf(dev, "Versatile PCI core not found\n");
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return (ENXIO);
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}
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sc->pcib_slot = slot;
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device_printf(dev, "PCI core at slot #%d\n", slot);
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versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
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val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
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val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
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versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
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/* Again SDRAM start >> 28 */
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versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
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versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
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versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
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/* Prepare resource managers */
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sc->mem_rman.rm_type = RMAN_ARRAY;
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sc->mem_rman.rm_descr = "versatile PCI memory window";
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if (rman_init(&sc->mem_rman) != 0 ||
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rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW,
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PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
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panic("versatile_pci_attach: failed to set up memory rman");
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}
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bootverbose = 1;
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sc->io_rman.rm_type = RMAN_ARRAY;
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sc->io_rman.rm_descr = "versatile PCI IO window";
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if (rman_init(&sc->io_rman) != 0 ||
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rman_manage_region(&sc->io_rman, PCI_IO_WINDOW,
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PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
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panic("versatile_pci_attach: failed to set up I/O rman");
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}
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sc->irq_rman.rm_type = RMAN_ARRAY;
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sc->irq_rman.rm_descr = "versatile PCI IRQs";
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if (rman_init(&sc->irq_rman) != 0 ||
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rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START,
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VERSATILE_PCI_IRQ_END) != 0) {
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panic("versatile_pci_attach: failed to set up IRQ rman");
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}
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mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
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MTX_SPIN);
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val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
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class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
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if (slot == sc->pcib_slot)
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continue;
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if ((vendordev_id == 0xffffffff) &&
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(class_id == 0xffffffff))
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continue;
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val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
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val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
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}
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ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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versatile_pci_read_ivar(device_t dev, device_t child, int which,
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uintptr_t *result)
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{
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struct versatile_pci_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->busno;
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return (0);
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}
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return (ENOENT);
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}
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static int
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versatile_pci_write_ivar(device_t dev, device_t child, int which,
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uintptr_t result)
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{
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struct versatile_pci_softc * sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->busno = result;
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return (0);
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}
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return (ENOENT);
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}
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static struct resource *
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versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct versatile_pci_softc *sc = device_get_softc(bus);
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struct resource *rv;
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struct rman *rm;
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dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
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switch (type) {
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case SYS_RES_IOPORT:
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rm = &sc->io_rman;
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break;
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case SYS_RES_IRQ:
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rm = NULL;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->mem_rman;
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break;
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default:
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return (NULL);
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}
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if (rm == NULL)
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return (BUS_ALLOC_RESOURCE(device_get_parent(bus),
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child, type, rid, start, end, count, flags));
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rv = rman_reserve_resource(rm, start, end, count, flags, child);
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if (rv == NULL)
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return (NULL);
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rman_set_rid(rv, *rid);
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, rv)) {
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rman_release_resource(rv);
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return (NULL);
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}
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}
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return (rv);
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}
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static int
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versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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vm_offset_t vaddr;
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int res;
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switch(type) {
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case SYS_RES_MEMORY:
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case SYS_RES_IOPORT:
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vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
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rman_get_size(r));
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rman_set_bushandle(r, vaddr);
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rman_set_bustag(r, fdtbus_bs_tag);
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res = rman_activate_resource(r);
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break;
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case SYS_RES_IRQ:
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res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
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child, type, rid, r));
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break;
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default:
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res = ENXIO;
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break;
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}
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return (res);
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}
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static int
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versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *handler,
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void *arg, void **cookiep)
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{
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return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
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filt, handler, arg, cookiep);
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}
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static int
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versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
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void *cookie)
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{
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return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
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}
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static int
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versatile_pci_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static int
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versatile_pci_route_interrupt(device_t bus, device_t dev, int pin)
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{
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struct versatile_pci_softc *sc;
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struct ofw_pci_register reg;
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uint32_t pintr, mintr[4];
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phandle_t iparent;
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int intrcells;
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sc = device_get_softc(bus);
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pintr = pin;
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bzero(®, sizeof(reg));
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reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
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(pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
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(pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
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intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
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&sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
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mintr, sizeof(mintr), &iparent);
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if (intrcells) {
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pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
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return (pintr);
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}
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device_printf(bus, "could not route pin %d for device %d.%d\n",
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pin, pci_get_slot(dev), pci_get_function(dev));
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return (PCI_INVALID_IRQ);
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}
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static uint32_t
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versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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struct versatile_pci_softc *sc = device_get_softc(dev);
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uint32_t data;
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uint32_t shift, mask;
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uint32_t addr;
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if (sc->pcib_slot == slot) {
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switch (bytes) {
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case 4:
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return (0xffffffff);
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break;
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case 2:
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return (0xffff);
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break;
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case 1:
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return (0xff);
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break;
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}
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}
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addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
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/* register access is 32-bit aligned */
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shift = (reg & 3) * 8;
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/* Create a mask based on the width, post-shift */
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if (bytes == 2)
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mask = 0xffff;
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else if (bytes == 1)
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mask = 0xff;
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else
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mask = 0xffffffff;
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dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
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func, reg, bytes);
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mtx_lock_spin(&sc->mtx);
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data = versatile_pci_conf_read_4(addr);
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mtx_unlock_spin(&sc->mtx);
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/* get request bytes from 32-bit word */
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data = (data >> shift) & mask;
|
|
|
|
dprintf("%s: read 0x%x\n", __func__, data);
|
|
|
|
return (data);
|
|
}
|
|
|
|
static void
|
|
versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
|
u_int reg, uint32_t data, int bytes)
|
|
{
|
|
|
|
struct versatile_pci_softc *sc = device_get_softc(dev);
|
|
uint32_t addr;
|
|
|
|
dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
|
|
func, reg, bytes);
|
|
|
|
if (sc->pcib_slot == slot)
|
|
return;
|
|
|
|
addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
|
|
mtx_lock_spin(&sc->mtx);
|
|
switch (bytes) {
|
|
case 4:
|
|
versatile_pci_conf_write_4(addr, data);
|
|
break;
|
|
case 2:
|
|
versatile_pci_conf_write_2(addr, data);
|
|
break;
|
|
case 1:
|
|
versatile_pci_conf_write_1(addr, data);
|
|
break;
|
|
}
|
|
mtx_unlock_spin(&sc->mtx);
|
|
}
|
|
|
|
static device_method_t versatile_pci_methods[] = {
|
|
DEVMETHOD(device_probe, versatile_pci_probe),
|
|
DEVMETHOD(device_attach, versatile_pci_attach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, versatile_pci_maxslots),
|
|
DEVMETHOD(pcib_read_config, versatile_pci_read_config),
|
|
DEVMETHOD(pcib_write_config, versatile_pci_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
|
|
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t versatile_pci_driver = {
|
|
"pcib",
|
|
versatile_pci_methods,
|
|
sizeof(struct versatile_pci_softc),
|
|
};
|
|
|
|
static devclass_t versatile_pci_devclass;
|
|
|
|
DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);
|