4eb4bc749d
- XLS B0 and later revision chips have PCIe link 2 & 3 mapped to different PIC interrupts. Update pic.h, board.h and xlr_pci.c to reflect this. - remove debug prints in xlr_pci.c - add more processor IDs to board.h, add function xlr_is_xls_b0() - some style(9) and whitespace fixes
273 lines
9.1 KiB
C
273 lines
9.1 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD
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* $FreeBSD$
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*/
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#ifndef _RMI_PIC_H_
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#define _RMI_PIC_H_
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#include <sys/cdefs.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <mips/rmi/iomap.h>
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#define PIC_IRT_WD_INDEX 0
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#define PIC_IRT_TIMER_INDEX(i) (1 + (i))
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#define PIC_IRT_UART_0_INDEX 9
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#define PIC_IRT_UART_1_INDEX 10
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#define PIC_IRT_I2C_0_INDEX 11
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#define PIC_IRT_I2C_1_INDEX 12
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#define PIC_IRT_PCMCIA_INDEX 13
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#define PIC_IRT_GPIO_INDEX 14
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#define PIC_IRT_HYPER_INDEX 15
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#define PIC_IRT_PCIX_INDEX 16
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#define PIC_IRT_GMAC0_INDEX 17
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#define PIC_IRT_GMAC1_INDEX 18
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#define PIC_IRT_GMAC2_INDEX 19
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#define PIC_IRT_GMAC3_INDEX 20
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#define PIC_IRT_XGS0_INDEX 21
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#define PIC_IRT_XGS1_INDEX 22
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#define PIC_IRT_HYPER_FATAL_INDEX 23
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#define PIC_IRT_PCIX_FATAL_INDEX 24
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#define PIC_IRT_BRIDGE_AERR_INDEX 25
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#define PIC_IRT_BRIDGE_BERR_INDEX 26
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#define PIC_IRT_BRIDGE_TB_INDEX 27
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#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
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/* numbering for XLS */
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#define PIC_IRT_BRIDGE_ERR_INDEX 25
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#define PIC_IRT_PCIE_LINK0_INDEX 26
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#define PIC_IRT_PCIE_LINK1_INDEX 27
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#define PIC_IRT_PCIE_LINK2_INDEX 23
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#define PIC_IRT_PCIE_LINK3_INDEX 24
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#define PIC_IRT_PCIE_B0_LINK2_INDEX 28
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#define PIC_IRT_PCIE_B0_LINK3_INDEX 29
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#define PIC_IRT_PCIE_INT_INDEX 28
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#define PIC_IRT_PCIE_FATAL_INDEX 29
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#define PIC_IRT_GPIO_B_INDEX 30
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#define PIC_IRT_USB_INDEX 31
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#define PIC_NUM_IRTS 32
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#define PIC_CLOCK_TIMER 7
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#define PIC_CTRL 0x00
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#define PIC_IPI 0x04
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#define PIC_INT_ACK 0x06
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#define WD_MAX_VAL_0 0x08
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#define WD_MAX_VAL_1 0x09
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#define WD_MASK_0 0x0a
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#define WD_MASK_1 0x0b
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#define WD_HEARBEAT_0 0x0c
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#define WD_HEARBEAT_1 0x0d
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#define PIC_IRT_0_BASE 0x40
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#define PIC_IRT_1_BASE 0x80
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#define PIC_TIMER_MAXVAL_0_BASE 0x100
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#define PIC_TIMER_MAXVAL_1_BASE 0x110
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#define PIC_TIMER_COUNT_0_BASE 0x120
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#define PIC_TIMER_COUNT_1_BASE 0x130
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#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
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#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
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#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
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#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
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#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
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#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
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#define PIC_TIMER_HZ 66000000U
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/*
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* We use a simple mapping form PIC interrupts to CPU IRQs.
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* The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
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* this leaves the lower 0-7 for the cpu interrupts (like
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* count/compare, msgrng) and 40-63 for IPIs
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*/
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#define PIC_IRQ_BASE 8
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#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
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#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
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#define PIC_WD_IRQ (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
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#define PIC_TIMER_IRQ(i) (PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
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#define PIC_CLOCK_IRQ PIC_TIMER_IRQ(PIC_CLOCK_TIMER)
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#define PIC_UART_0_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
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#define PIC_UART_1_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
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#define PIC_I2C_0_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
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#define PIC_I2C_1_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
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#define PIC_PCMCIA_IRQ (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
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#define PIC_GPIO_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
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#define PIC_HYPER_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
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#define PIC_PCIX_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
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#define PIC_GMAC_0_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
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#define PIC_GMAC_1_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
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#define PIC_GMAC_2_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
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#define PIC_GMAC_3_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
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#define PIC_XGS_0_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
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#define PIC_XGS_1_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
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#define PIC_HYPER_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
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#define PIC_PCIX_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
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#define PIC_BRIDGE_AERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
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#define PIC_BRIDGE_BERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
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#define PIC_BRIDGE_TB_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
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#define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
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#define PIC_BRIDGE_ERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
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#define PIC_PCIE_LINK0_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
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#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
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#define PIC_PCIE_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
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#define PIC_PCIE_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
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#define PIC_PCIE_B0_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK2_INDEX)
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#define PIC_PCIE_B0_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK3_INDEX)
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#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT_INDEX)
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#define PIC_PCIE_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
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#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
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#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
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#define PIC_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \
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(irq) < PIC_IRQ_BASE + PIC_NUM_IRTS)
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#define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) && \
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(i) <= PIC_IRT_TIMER_INDEX(7))
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extern struct mtx xlr_pic_lock;
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static __inline uint32_t
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pic_read_control(void)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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uint32_t reg;
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mtx_lock_spin(&xlr_pic_lock);
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xlr_read_reg(mmio, PIC_CTRL);
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mtx_unlock_spin(&xlr_pic_lock);
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return (reg);
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}
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static __inline void
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pic_write_control(uint32_t control)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_CTRL, control);
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mtx_unlock_spin(&xlr_pic_lock);
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}
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static __inline void
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pic_update_control(__uint32_t control)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
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mtx_unlock_spin(&xlr_pic_lock);
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}
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static __inline void
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pic_ack(int picintr)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
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}
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static __inline
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void pic_send_ipi(int cpu, int ipi)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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int tid, pid;
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tid = cpu & 0x3;
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pid = (cpu >> 2) & 0x7;
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xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
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}
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static __inline
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void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
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xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) |
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(1 << 6) | irq));
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mtx_unlock_spin(&xlr_pic_lock);
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}
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static __inline void
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pic_init_timer(int timer)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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uint32_t val;
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mtx_lock_spin(&xlr_pic_lock);
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val = xlr_read_reg(mmio, PIC_CTRL);
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val |= (1 << (8 + timer));
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xlr_write_reg(mmio, PIC_CTRL, val);
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mtx_unlock_spin(&xlr_pic_lock);
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}
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static __inline void
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pic_set_timer(int timer, uint64_t maxval)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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xlr_write_reg(mmio, PIC_TIMER_MAXVAL_0(timer),
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(maxval & 0xffffffff));
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xlr_write_reg(mmio, PIC_TIMER_MAXVAL_1(timer),
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(maxval >> 32) & 0xffffffff);
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}
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static __inline uint32_t
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pic_timer_count32(int timer)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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return (xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)));
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}
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/*
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* The timer can wrap 32 bits between the two reads, so we
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* need additional logic to detect that.
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*/
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static __inline uint64_t
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pic_timer_count(int timer)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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uint32_t tu1, tu2, tl;
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tu1 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
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tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
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tu2 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
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if (tu2 != tu1)
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tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
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return (((uint64_t)tu2 << 32) | tl);
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}
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#endif /* _RMI_PIC_H_ */
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