ce9844cd72
Convert PCIe hot plug support over to asking the firmware, if any, for permission to use the HotPlug hardware. Implement pci_request_feature for ACPI. All other host pci connections to allowing all valid feature requests. Sponsored by: Netflix
558 lines
15 KiB
C
558 lines
15 KiB
C
/* $NetBSD: idtpci.c,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 David Young.
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* Copyright (c) 2007 Oleskandr Tymoshenko. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <mips/idt/idtreg.h>
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#ifdef IDTPCI_DEBUG
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int idtpci_debug = 1;
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#define IDTPCI_DPRINTF(__fmt, ...) \
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do { \
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if (idtpci_debug) \
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printf((__fmt), __VA_ARGS__); \
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} while (/*CONSTCOND*/0)
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#else /* !IDTPCI_DEBUG */
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#define IDTPCI_DPRINTF(__fmt, ...) do { } while (/*CONSTCOND*/0)
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#endif /* IDTPCI_DEBUG */
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#define IDTPCI_TAG_BUS_MASK 0x007f0000
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#define IDTPCI_TAG_DEVICE_MASK 0x00007800
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#define IDTPCI_TAG_FUNCTION_MASK 0x00000300
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#define IDTPCI_TAG_REGISTER_MASK 0x0000007c
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#define IDTPCI_MAX_DEVICE
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#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_PCI + (o)))
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#define REG_WRITE(o,v) (REG_READ(o)) = (v)
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unsigned int korina_fixup[24] = {
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0x00000157, 0x00000000, 0x00003c04, 0x00000008, 0x18800001, 0x18000001,
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0x48000008, 0x00000000, 0x00000000, 0x00000000, 0x011d0214, 0x00000000,
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0x00000000, 0x00000000, 0x38080101, 0x00008080, 0x00000d6e, 0x00000000,
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0x00000051, 0x00000000, 0x00000055, 0x18000000, 0x00000000, 0x00000000
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};
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struct idtpci_softc {
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device_t sc_dev;
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int sc_busno;
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struct rman sc_mem_rman[2];
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struct rman sc_io_rman[2];
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struct rman sc_irq_rman;
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};
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static uint32_t
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idtpci_make_addr(int bus, int slot, int func, int reg)
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{
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return 0x80000000 | (bus << 16) | (slot << 11) | (func << 8) | reg;
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}
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static int
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idtpci_probe(device_t dev)
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{
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return (0);
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}
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static int
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idtpci_attach(device_t dev)
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{
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int busno = 0;
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struct idtpci_softc *sc = device_get_softc(dev);
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unsigned int pci_data, force_endianess = 0;
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int i;
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bus_addr_t addr;
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sc->sc_dev = dev;
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sc->sc_busno = busno;
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/* TODO: Check for host mode */
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/* Enabled PCI, IG mode, EAP mode */
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REG_WRITE(IDT_PCI_CNTL, IDT_PCI_CNTL_IGM | IDT_PCI_CNTL_EAP |
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IDT_PCI_CNTL_EN);
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/* Wait while "Reset in progress bit" set */
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while(1) {
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pci_data = REG_READ(IDT_PCI_STATUS);
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if((pci_data & IDT_PCI_STATUS_RIP) == 0)
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break;
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}
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/* Reset status register */
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REG_WRITE(IDT_PCI_STATUS, 0);
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/* Mask interrupts related to status register */
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REG_WRITE(IDT_PCI_STATUS_MASK, 0xffffffff);
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/* Disable PCI decoupled access */
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REG_WRITE(IDT_PCI_DAC, 0);
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/* Zero status and mask DA interrupts */
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REG_WRITE(IDT_PCI_DAS, 0);
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REG_WRITE(IDT_PCI_DASM, 0x7f);
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/* Init PCI messaging unit */
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/* Disable messaging interrupts */
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REG_WRITE(IDT_PCI_IIC, 0);
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REG_WRITE(IDT_PCI_IIM, 0xffffffff);
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REG_WRITE(IDT_PCI_OIC, 0);
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REG_WRITE(IDT_PCI_OIM, 0);
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#ifdef __MIPSEB__
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force_endianess = IDT_PCI_LBA_FE;
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#endif
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/* LBA0 -- memory window */
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REG_WRITE(IDT_PCI_LBA0, IDT_PCIMEM0_BASE);
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REG_WRITE(IDT_PCI_LBA0_MAP, IDT_PCIMEM0_BASE);
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REG_WRITE(IDT_PCI_LBA0_CNTL, IDT_PCI_LBA_SIZE_16MB | force_endianess);
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pci_data = REG_READ(IDT_PCI_LBA0_CNTL);
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/* LBA1 -- memory window */
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REG_WRITE(IDT_PCI_LBA1, IDT_PCIMEM1_BASE);
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REG_WRITE(IDT_PCI_LBA1_MAP, IDT_PCIMEM1_BASE);
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REG_WRITE(IDT_PCI_LBA1_CNTL, IDT_PCI_LBA_SIZE_256MB | force_endianess);
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pci_data = REG_READ(IDT_PCI_LBA1_CNTL);
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/* LBA2 -- IO window */
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REG_WRITE(IDT_PCI_LBA2, IDT_PCIMEM2_BASE);
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REG_WRITE(IDT_PCI_LBA2_MAP, IDT_PCIMEM2_BASE);
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REG_WRITE(IDT_PCI_LBA2_CNTL, IDT_PCI_LBA_SIZE_4MB | IDT_PCI_LBA_MSI |
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force_endianess);
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pci_data = REG_READ(IDT_PCI_LBA2_CNTL);
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/* LBA3 -- IO window */
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REG_WRITE(IDT_PCI_LBA3, IDT_PCIMEM3_BASE);
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REG_WRITE(IDT_PCI_LBA3_MAP, IDT_PCIMEM3_BASE);
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REG_WRITE(IDT_PCI_LBA3_CNTL, IDT_PCI_LBA_SIZE_1MB | IDT_PCI_LBA_MSI |
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force_endianess);
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pci_data = REG_READ(IDT_PCI_LBA3_CNTL);
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pci_data = REG_READ(IDT_PCI_CNTL) & ~IDT_PCI_CNTL_TNR;
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REG_WRITE(IDT_PCI_CNTL, pci_data);
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pci_data = REG_READ(IDT_PCI_CNTL);
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/* Rewrite Target Control register with default values */
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REG_WRITE(IDT_PCI_TC, (IDT_PCI_TC_DTIMER << 8) | IDT_PCI_TC_RTIMER);
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/* Perform Korina fixup */
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addr = idtpci_make_addr(0, 0, 0, 4);
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for (i = 0; i < 24; i++) {
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REG_WRITE(IDT_PCI_CFG_ADDR, addr);
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REG_WRITE(IDT_PCI_CFG_DATA, korina_fixup[i]);
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__asm__ volatile ("sync");
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REG_WRITE(IDT_PCI_CFG_ADDR, 0);
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REG_WRITE(IDT_PCI_CFG_DATA, 0);
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addr += 4;
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}
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/* Use KSEG1 to access IO ports for it is uncached */
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sc->sc_io_rman[0].rm_type = RMAN_ARRAY;
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sc->sc_io_rman[0].rm_descr = "IDTPCI I/O Ports window 1";
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if (rman_init(&sc->sc_io_rman[0]) != 0 ||
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rman_manage_region(&sc->sc_io_rman[0],
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IDT_PCIMEM2_BASE, IDT_PCIMEM2_BASE + IDT_PCIMEM2_SIZE - 1) != 0) {
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panic("idtpci_attach: failed to set up I/O rman");
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}
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sc->sc_io_rman[1].rm_type = RMAN_ARRAY;
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sc->sc_io_rman[1].rm_descr = "IDTPCI I/O Ports window 2";
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if (rman_init(&sc->sc_io_rman[1]) != 0 ||
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rman_manage_region(&sc->sc_io_rman[1],
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IDT_PCIMEM3_BASE, IDT_PCIMEM3_BASE + IDT_PCIMEM3_SIZE - 1) != 0) {
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panic("idtpci_attach: failed to set up I/O rman");
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}
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/* Use KSEG1 to access PCI memory for it is uncached */
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sc->sc_mem_rman[0].rm_type = RMAN_ARRAY;
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sc->sc_mem_rman[0].rm_descr = "IDTPCI PCI Memory window 1";
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if (rman_init(&sc->sc_mem_rman[0]) != 0 ||
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rman_manage_region(&sc->sc_mem_rman[0],
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IDT_PCIMEM0_BASE, IDT_PCIMEM0_BASE + IDT_PCIMEM0_SIZE) != 0) {
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panic("idtpci_attach: failed to set up memory rman");
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}
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sc->sc_mem_rman[1].rm_type = RMAN_ARRAY;
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sc->sc_mem_rman[1].rm_descr = "IDTPCI PCI Memory window 2";
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if (rman_init(&sc->sc_mem_rman[1]) != 0 ||
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rman_manage_region(&sc->sc_mem_rman[1],
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IDT_PCIMEM1_BASE, IDT_PCIMEM1_BASE + IDT_PCIMEM1_SIZE) != 0) {
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panic("idtpci_attach: failed to set up memory rman");
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}
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "IDTPCI PCI IRQs";
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, PCI_IRQ_BASE,
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PCI_IRQ_END) != 0)
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panic("idtpci_attach: failed to set up IRQ rman");
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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idtpci_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static uint32_t
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idtpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int bytes)
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{
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uint32_t data;
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uint32_t shift, mask;
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bus_addr_t addr;
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IDTPCI_DPRINTF("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__,
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bus, slot, func, reg, bytes);
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addr = idtpci_make_addr(bus, slot, func, reg);
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REG_WRITE(IDT_PCI_CFG_ADDR, addr);
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data = REG_READ(IDT_PCI_CFG_DATA);
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switch (reg % 4) {
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case 3:
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shift = 24;
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break;
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case 2:
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shift = 16;
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break;
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case 1:
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shift = 8;
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break;
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default:
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shift = 0;
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break;
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}
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switch (bytes) {
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case 1:
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mask = 0xff;
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data = (data >> shift) & mask;
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break;
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case 2:
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mask = 0xffff;
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if (reg % 4 == 0)
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data = data & mask;
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else
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data = (data >> 16) & mask;
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break;
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case 4:
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break;
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default:
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panic("%s: wrong bytes count", __func__);
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break;
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}
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__asm__ volatile ("sync");
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IDTPCI_DPRINTF("%s: read 0x%x\n", __func__, data);
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return (data);
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}
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static void
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idtpci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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uint32_t data, int bytes)
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{
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bus_addr_t addr;
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uint32_t reg_data;
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uint32_t shift, mask;
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IDTPCI_DPRINTF("%s: tag (%x, %x, %x) reg %d(%d) data %08x\n", __func__,
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bus, slot, func, reg, bytes, data);
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if (bytes != 4) {
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reg_data = idtpci_read_config(dev, bus, slot, func, reg, 4);
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switch (reg % 4) {
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case 3:
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shift = 24;
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break;
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case 2:
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shift = 16;
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break;
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case 1:
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shift = 8;
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break;
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default:
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shift = 0;
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break;
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}
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switch (bytes) {
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case 1:
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mask = 0xff;
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data = (reg_data & ~ (mask << shift)) | (data << shift);
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break;
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case 2:
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mask = 0xffff;
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if (reg % 4 == 0)
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data = (reg_data & ~mask) | data;
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else
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data = (reg_data & ~ (mask << shift)) |
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(data << shift);
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break;
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case 4:
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break;
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default:
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panic("%s: wrong bytes count", __func__);
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break;
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}
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}
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addr = idtpci_make_addr(bus, slot, func, reg);
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REG_WRITE(IDT_PCI_CFG_ADDR, addr);
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REG_WRITE(IDT_PCI_CFG_DATA, data);
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__asm__ volatile ("sync");
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REG_WRITE(IDT_PCI_CFG_ADDR, 0);
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REG_WRITE(IDT_PCI_CFG_DATA, 0);
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}
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static int
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idtpci_route_interrupt(device_t pcib, device_t device, int pin)
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{
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static int idt_pci_table[2][12] =
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{
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{ 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
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{ 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
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};
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int dev, bus, irq;
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dev = pci_get_slot(device);
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bus = pci_get_bus(device);
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if (bootverbose)
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device_printf(pcib, "routing pin %d for %s\n", pin,
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device_get_nameunit(device));
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if (bus >= 0 && bus <= 1 &&
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dev >= 0 && dev <= 11) {
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irq = IP_IRQ(6, idt_pci_table[bus][dev] + 4);
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if (bootverbose)
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printf("idtpci: %d/%d/%d -> IRQ%d\n",
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pci_get_bus(device), dev, pci_get_function(device),
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irq);
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return (irq);
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} else
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printf("idtpci: no mapping for %d/%d/%d\n",
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pci_get_bus(device), dev, pci_get_function(device));
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return (-1);
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}
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static int
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idtpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct idtpci_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->sc_busno;
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return (0);
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}
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return (ENOENT);
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}
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static int
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idtpci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
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{
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struct idtpci_softc * sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->sc_busno = result;
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return (0);
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}
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return (ENOENT);
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}
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static struct resource *
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idtpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct idtpci_softc *sc = device_get_softc(bus);
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struct resource *rv = NULL;
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struct rman *rm1, *rm2;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IRQ:
|
|
rm1 = &sc->sc_irq_rman;
|
|
rm2 = NULL;
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rm1 = &sc->sc_mem_rman[0];
|
|
rm2 = &sc->sc_mem_rman[1];
|
|
break;
|
|
case SYS_RES_IOPORT:
|
|
rm1 = &sc->sc_io_rman[0];
|
|
rm2 = &sc->sc_io_rman[1];
|
|
break;
|
|
default:
|
|
return (NULL);
|
|
}
|
|
|
|
rv = rman_reserve_resource(rm1, start, end, count, flags, child);
|
|
|
|
/* Try second window if it exists */
|
|
if ((rv == NULL) && (rm2 != NULL))
|
|
rv = rman_reserve_resource(rm2, start, end, count, flags,
|
|
child);
|
|
|
|
if (rv == NULL)
|
|
return (NULL);
|
|
|
|
rman_set_rid(rv, *rid);
|
|
|
|
if (flags & RF_ACTIVE) {
|
|
if (bus_activate_resource(child, type, *rid, rv)) {
|
|
rman_release_resource(rv);
|
|
return (NULL);
|
|
}
|
|
}
|
|
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
idtpci_teardown_intr(device_t dev, device_t child, struct resource *res,
|
|
void *cookie)
|
|
{
|
|
|
|
return (intr_event_remove_handler(cookie));
|
|
}
|
|
|
|
static device_method_t idtpci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, idtpci_probe),
|
|
DEVMETHOD(device_attach, idtpci_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, idtpci_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, idtpci_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, idtpci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, idtpci_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, idtpci_maxslots),
|
|
DEVMETHOD(pcib_read_config, idtpci_read_config),
|
|
DEVMETHOD(pcib_write_config, idtpci_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, idtpci_route_interrupt),
|
|
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t idtpci_driver = {
|
|
"pcib",
|
|
idtpci_methods,
|
|
sizeof(struct idtpci_softc),
|
|
};
|
|
|
|
static devclass_t idtpci_devclass;
|
|
|
|
DRIVER_MODULE(idtpci, obio, idtpci_driver, idtpci_devclass, 0, 0);
|