freebsd-skq/sys/arm
ian 39e8e58c20 Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.

In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.

These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.

In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.

Differential Revision:	https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
..
allwinner Add gpio methods to read/write/configure up to 32 pins simultaneously. 2017-09-10 18:08:25 +00:00
altera/socfpga
amlogic/aml8726
annapurna/alpine
arm Disable the ARM generic timers before interrupts are enabled. Some 2017-09-03 09:41:40 +00:00
at91 Rename at91_pmc's M_PMC malloc type to avoid duplicate definition 2017-08-11 18:09:26 +00:00
broadcom/bcm2835 Change leading spaces to tabs, no functional change. 2017-09-02 19:22:16 +00:00
cavium/cns11xx
cloudabi32
conf Change name of Marvell Armada38x RTC driver 2017-09-05 05:42:37 +00:00
freescale Add gpio methods to read/write/configure up to 32 pins simultaneously. 2017-09-10 18:08:25 +00:00
include Fix TEX index acquisition using L2 attributes 2017-07-27 23:14:17 +00:00
lpc
mv Add Armada 80x0/70x0 compatible to 38x RTC driver 2017-09-05 05:45:57 +00:00
nvidia
qemu
ralink
rockchip
samsung/exynos
ti Ensure the clocks driver is attached before any drivers that need to enable 2017-08-10 19:42:30 +00:00
versatile
xilinx Add external PLATFORM access on arm, and use it in the pl310 driver. 2017-07-11 16:30:16 +00:00
xscale