a8b6bed223
all of the features in the current working draft of the upcoming C++ standard, provisionally named C++1y. The code generator's performance is greatly increased, and the loop auto-vectorizer is now enabled at -Os and -O2 in addition to -O3. The PowerPC backend has made several major improvements to code generation quality and compile time, and the X86, SPARC, ARM32, Aarch64 and SystemZ backends have all seen major feature work. Release notes for llvm and clang can be found here: <http://llvm.org/releases/3.4/docs/ReleaseNotes.html> <http://llvm.org/releases/3.4/tools/clang/docs/ReleaseNotes.html> MFC after: 1 month
57 lines
1.9 KiB
C++
57 lines
1.9 KiB
C++
//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/ADT/SmallVector.h"
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using namespace llvm;
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//---------------------------------------------------------------------------
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// TargetSubtargetInfo Class
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//
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TargetSubtargetInfo::TargetSubtargetInfo() {}
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TargetSubtargetInfo::~TargetSubtargetInfo() {}
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// Temporary option to compare overall performance change when moving from the
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// SD scheduler to the MachineScheduler pass pipeline. It should be removed
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// before 3.4. The normal way to enable/disable the MachineScheduling pass
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// itself is by using -enable-misched. For targets that already use MI sched
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// (via MySubTarget::enableMachineScheduler()) -misched-bench=false negates the
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// subtarget hook.
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static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
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cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
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bool TargetSubtargetInfo::useMachineScheduler() const {
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if (BenchMachineSched.getNumOccurrences())
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return BenchMachineSched;
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = ANTIDEP_NONE;
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CriticalPathRCs.clear();
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return false;
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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