ce0b215965
applied to our copy of llvm/clang. These can be applied in alphabetical order to a pristine llvm/clang 3.4 release source tree, to result in the same version used in FreeBSD. This is intended to clearly document all the changes until now, which mostly consist of cherry pickings from the respective upstream trunks, plus a number of hand-written FreeBSD-specific ones. Hopefully those can eventually be cleaned up and sent upstream too. MFC after: 1 week X-MFC-With: r263313
116 lines
5.1 KiB
Diff
116 lines
5.1 KiB
Diff
Pull in r198740 from upstream llvm trunk (by Venkatraman Govindaraju):
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[SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
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Introduced here: http://svn.freebsd.org/changeset/base/262261
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Index: test/MC/Sparc/sparc64-alu-instructions.s
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===================================================================
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--- test/MC/Sparc/sparc64-alu-instructions.s
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+++ test/MC/Sparc/sparc64-alu-instructions.s
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@@ -0,0 +1,38 @@
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+! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s
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+
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+ ! CHECK: sllx %g1, %i2, %i0 ! encoding: [0xb1,0x28,0x50,0x1a]
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+ sllx %g1, %i2, %i0
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+
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+ ! CHECK: sllx %g1, 63, %i0 ! encoding: [0xb1,0x28,0x70,0x3f]
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+ sllx %g1, 63, %i0
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+
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+ ! CHECK: srlx %g1, %i2, %i0 ! encoding: [0xb1,0x30,0x50,0x1a]
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+ srlx %g1, %i2, %i0
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+
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+ ! CHECK: srlx %g1, 63, %i0 ! encoding: [0xb1,0x30,0x70,0x3f]
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+ srlx %g1, 63, %i0
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+
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+ ! CHECK: srax %g1, %i2, %i0 ! encoding: [0xb1,0x38,0x50,0x1a]
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+ srax %g1, %i2, %i0
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+
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+ ! CHECK: srax %g1, 63, %i0 ! encoding: [0xb1,0x38,0x70,0x3f]
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+ srax %g1, 63, %i0
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+
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+ ! CHECK: mulx %g1, %i2, %i0 ! encoding: [0xb0,0x48,0x40,0x1a]
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+ mulx %g1, %i2, %i0
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+
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+ ! CHECK: mulx %g1, 63, %i0 ! encoding: [0xb0,0x48,0x60,0x3f]
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+ mulx %g1, 63, %i0
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+
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+ ! CHECK: sdivx %g1, %i2, %i0 ! encoding: [0xb1,0x68,0x40,0x1a]
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+ sdivx %g1, %i2, %i0
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+
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+ ! CHECK: sdivx %g1, 63, %i0 ! encoding: [0xb1,0x68,0x60,0x3f]
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+ sdivx %g1, 63, %i0
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+
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+ ! CHECK: udivx %g1, %i2, %i0 ! encoding: [0xb0,0x68,0x40,0x1a]
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+ udivx %g1, %i2, %i0
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+
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+ ! CHECK: udivx %g1, 63, %i0 ! encoding: [0xb0,0x68,0x60,0x3f]
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+ udivx %g1, 63, %i0
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+
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Index: lib/Target/Sparc/SparcInstr64Bit.td
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===================================================================
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--- lib/Target/Sparc/SparcInstr64Bit.td
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+++ lib/Target/Sparc/SparcInstr64Bit.td
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@@ -193,9 +193,9 @@ def MULXrr : F3_1<2, 0b001001,
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"mulx $rs1, $rs2, $rd",
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[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
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def MULXri : F3_2<2, 0b001001,
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- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
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- "mulx $rs1, $i, $rd",
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- [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
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+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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+ "mulx $rs1, $simm13, $rd",
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+ [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
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// Division can trap.
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let hasSideEffects = 1 in {
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@@ -204,9 +204,9 @@ def SDIVXrr : F3_1<2, 0b101101,
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"sdivx $rs1, $rs2, $rd",
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[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
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def SDIVXri : F3_2<2, 0b101101,
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- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
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- "sdivx $rs1, $i, $rd",
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- [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
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+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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+ "sdivx $rs1, $simm13, $rd",
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+ [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
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def UDIVXrr : F3_1<2, 0b001101,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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@@ -213,9 +213,9 @@ def UDIVXrr : F3_1<2, 0b001101,
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"udivx $rs1, $rs2, $rd",
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[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
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def UDIVXri : F3_2<2, 0b001101,
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- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
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- "udivx $rs1, $i, $rd",
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- [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
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+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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+ "udivx $rs1, $simm13, $rd",
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+ [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
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} // hasSideEffects = 1
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} // Predicates = [Is64Bit]
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Index: lib/Target/Sparc/SparcInstrFormats.td
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===================================================================
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--- lib/Target/Sparc/SparcInstrFormats.td
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+++ lib/Target/Sparc/SparcInstrFormats.td
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@@ -193,12 +193,12 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVa
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// Define rr and ri shift instructions with patterns.
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multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
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ValueType VT, RegisterClass RC> {
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- def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
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- !strconcat(OpcStr, " $rs, $rs2, $rd"),
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- [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
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- def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
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- !strconcat(OpcStr, " $rs, $shcnt, $rd"),
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- [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
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+ def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
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+ !strconcat(OpcStr, " $rs1, $rs2, $rd"),
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+ [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
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+ def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
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+ !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
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+ [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
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}
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class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
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