ce0b215965
applied to our copy of llvm/clang. These can be applied in alphabetical order to a pristine llvm/clang 3.4 release source tree, to result in the same version used in FreeBSD. This is intended to clearly document all the changes until now, which mostly consist of cherry pickings from the respective upstream trunks, plus a number of hand-written FreeBSD-specific ones. Hopefully those can eventually be cleaned up and sent upstream too. MFC after: 1 week X-MFC-With: r263313
61 lines
2.6 KiB
Diff
61 lines
2.6 KiB
Diff
Pull in r203311 from upstream llvm trunk (by Arnold Schwaighofer):
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ISel: Make VSELECT selection terminate in cases where the condition type has to
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be split and the result type widened.
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When the condition of a vselect has to be split it makes no sense widening the
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vselect and thereby widening the condition. We end up in an endless loop of
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widening (vselect result type) and splitting (condition mask type) doing this.
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Instead, split both the condition and the vselect and widen the result.
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I ran this over the test suite with i686 and mattr=+sse and saw no regressions.
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Fixes PR18036.
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Introduced here: http://svn.freebsd.org/changeset/base/263313
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Index: test/CodeGen/X86/sse1.ll
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===================================================================
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--- test/CodeGen/X86/sse1.ll
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+++ test/CodeGen/X86/sse1.ll
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@@ -43,3 +43,17 @@ entry:
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; CHECK-NOT: shufps $16
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; CHECK: ret
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}
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+
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+; We used to get stuck in type legalization for this example when lowering the
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+; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
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+; is not. We used to ping pong between splitting the vselect for the v4i
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+; condition operand and widening the resulting vselect for the v4f32 result.
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+; PR18036
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+
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+; CHECK-LABEL: vselect
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+define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) {
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+entry:
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+ %a1 = icmp eq <4 x i32> %q, zeroinitializer
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+ %a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer
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+ ret <4 x float> %a14
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+}
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Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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===================================================================
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--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@@ -2180,6 +2180,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNod
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if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
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Cond1 = GetWidenedVector(Cond1);
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+ // If we have to split the condition there is no point in widening the
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+ // select. This would result in an cycle of widening the select ->
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+ // widening the condition operand -> splitting the condition operand ->
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+ // splitting the select -> widening the select. Instead split this select
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+ // further and widen the resulting type.
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+ if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
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+ SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
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+ SDValue Res = ModifyToType(SplitSelect, WidenVT);
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+ return Res;
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+ }
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+
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if (Cond1.getValueType() != CondWidenVT)
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Cond1 = ModifyToType(Cond1, CondWidenVT);
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}
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