ad1e7d285a
Make part of John Birrell's KSE patch permanent.. Specifically, remove: Any reference of the ksegrp structure. This feature was never fully utilised and made things overly complicated. All code in the scheduler that tried to make threaded programs fair to unthreaded programs. Libpthread processes will already do this to some extent and libthr processes already disable it. Also: Since this makes such a big change to the scheduler(s), take the opportunity to rename some structures and elements that had to be moved anyhow. This makes the code a lot more readable. The ULE scheduler compiles again but I have no idea if it works. The 4bsd scheduler still reqires a little cleaning and some functions that now do ALMOST nothing will go away, but I thought I'd do that as a separate commit. Tested by David Xu, and Dan Eischen using libthr and libpthread.
498 lines
16 KiB
C
498 lines
16 KiB
C
/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* machdep.c
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*
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* Machine dependant functions for kernel setup
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*
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* This file needs a lot of work.
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*
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* Created : 17/09/94
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*/
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#include "opt_msgbuf.h"
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#include "opt_ddb.h"
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#include "opt_at91.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysproto.h>
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#include <sys/signalvar.h>
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#include <sys/imgact.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/linker.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/ptrace.h>
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#include <sys/cons.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/buf.h>
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#include <sys/exec.h>
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#include <sys/kdb.h>
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#include <sys/msgbuf.h>
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#include <machine/reg.h>
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#include <machine/cpu.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_pager.h>
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#include <vm/vm_map.h>
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#include <vm/vnode_pager.h>
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#include <machine/pmap.h>
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#include <machine/vmparam.h>
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#include <machine/pcb.h>
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#include <machine/undefined.h>
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#include <machine/machdep.h>
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#include <machine/metadata.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <sys/reboot.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91_piovar.h>
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#include <arm/at91/at91_pio_rm9200.h>
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#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
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#define KERNEL_PT_KERN 1
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#define KERNEL_PT_KERN_NUM 22
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#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
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#define KERNEL_PT_AFKERNEL_NUM 5
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/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
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#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
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/* Define various stack sizes in pages */
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#define IRQ_STACK_SIZE 1
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#define ABT_STACK_SIZE 1
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#define UND_STACK_SIZE 1
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extern u_int data_abort_handler_address;
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extern u_int prefetch_abort_handler_address;
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extern u_int undefined_handler_address;
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struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
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extern void *_end;
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extern int *end;
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struct pcpu __pcpu;
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struct pcpu *pcpup = &__pcpu;
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/* Physical and virtual addresses for some global pages */
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vm_paddr_t phys_avail[10];
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vm_paddr_t dump_avail[4];
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vm_offset_t physical_pages;
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struct pv_addr systempage;
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struct pv_addr msgbufpv;
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struct pv_addr irqstack;
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struct pv_addr undstack;
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struct pv_addr abtstack;
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struct pv_addr kernelstack;
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struct pv_addr minidataclean;
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static struct trapframe proc0_tf;
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/* Static device mappings. */
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static const struct pmap_devmap kb920x_devmap[] = {
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/*
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* Map the on-board devices VA == PA so that we can access them
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* with the MMU on or off.
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*/
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{
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/*
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* This at least maps the interrupt controller, the UART
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* and the timer. Other devices should use newbus to
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* map their memory anyway.
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*/
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0xdff00000,
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0xfff00000,
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0x100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/*
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* We can't just map the OHCI registers VA == PA, because
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* AT91RM92_OHCI_BASE belongs to the userland address space.
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* We could just choose a different virtual address, but a better
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* solution would probably be to just use pmap_mapdev() to allocate
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* KVA, as we don't need the OHCI controller before the vm
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* initialization is done. However, the AT91 resource allocation
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* system doesn't know how to use pmap_mapdev() yet.
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*/
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#if 0
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{
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/*
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* Add the ohci controller, and anything else that might be
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* on this chip select for a VA/PA mapping.
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*/
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AT91RM92_OHCI_BASE,
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AT91RM92_OHCI_BASE,
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AT91RM92_OHCI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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#endif
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{
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0,
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0,
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0,
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0,
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0,
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}
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};
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#define SDRAM_START 0xa0000000
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#ifdef DDB
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extern vm_offset_t ksym_start, ksym_end;
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#endif
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static long
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ramsize(void)
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{
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uint32_t *SDRAMC = (uint32_t *)(AT91RM92_BASE + AT91RM92_SDRAMC_BASE);
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uint32_t cr, mr;
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int banks, rows, cols, bw;
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cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
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mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
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bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
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banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
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rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
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return (1 << (cols + rows + banks + bw));
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}
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static long
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board_init(void)
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{
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/*
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* Since the USART supprots RS-485 multidrop mode, it allows the
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* TX pins to float. However, for RS-232 operations, we don't want
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* these pins to float. Instead, they should be pulled up to avoid
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* mismatches. Linux does something similar when it configures the
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* TX lines. This implies that we also allow the RX lines to float
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* rather than be in the state they are left in by the boot loader.
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* Since they are input pins, I think that this is the right thing
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* to do.
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*/
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/* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
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AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0);
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
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AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1);
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/* PIOA's B periph: Turn USART 3's TX/RX pins */
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at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0);
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at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1);
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#ifdef AT91_TSC
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/* We're using TC0's A1 and A2 input */
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at91_pio_use_periph_b(AT91RM92_PIOA_BASE,
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AT91C_PA19_TIOA1 | AT91C_PA21_TIOA2, 0);
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#endif
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/* PIOB's A periph: Turn USART 1's TX/RX pins */
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at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0);
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at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1);
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/* Pin assignment */
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#ifdef AT91_TSC
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/* Assert PA24 low -- talk to rubidium */
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at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
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at91_pio_gpio_output(AT91RM92_PIOA_BASE, AT91C_PIO_PA24, 0);
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at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
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at91_pio_use_gpio(AT91RM92_PIOB_BASE,
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AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19);
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#endif
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return (ramsize());
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}
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void *
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initarm(void *arg, void *arg2)
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{
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struct pv_addr kernel_l1pt;
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int loop;
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u_int l1pagetable;
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vm_offset_t freemempos;
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vm_offset_t afterkern;
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int i;
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uint32_t fake_preload[35];
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uint32_t memsize;
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vm_offset_t lastaddr;
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#ifdef DDB
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vm_offset_t zstart = 0, zend = 0;
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#endif
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i = 0;
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set_cpufuncs();
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fake_preload[i++] = MODINFO_NAME;
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fake_preload[i++] = strlen("elf kernel") + 1;
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strcpy((char*)&fake_preload[i++], "elf kernel");
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i += 2;
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fake_preload[i++] = MODINFO_TYPE;
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fake_preload[i++] = strlen("elf kernel") + 1;
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strcpy((char*)&fake_preload[i++], "elf kernel");
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i += 2;
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fake_preload[i++] = MODINFO_ADDR;
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fake_preload[i++] = sizeof(vm_offset_t);
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fake_preload[i++] = KERNBASE;
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fake_preload[i++] = MODINFO_SIZE;
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fake_preload[i++] = sizeof(uint32_t);
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fake_preload[i++] = (uint32_t)&end - KERNBASE;
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#ifdef DDB
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if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
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fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
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fake_preload[i++] = sizeof(vm_offset_t);
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fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
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fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
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fake_preload[i++] = sizeof(vm_offset_t);
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fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
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lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
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zend = lastaddr;
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zstart = *(uint32_t *)(KERNVIRTADDR + 4);
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ksym_start = zstart;
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ksym_end = zend;
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} else
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#endif
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lastaddr = (vm_offset_t)&end;
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fake_preload[i++] = 0;
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fake_preload[i] = 0;
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preload_metadata = (void *)fake_preload;
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pcpu_init(pcpup, 0, sizeof(struct pcpu));
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PCPU_SET(curthread, &thread0);
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#define KERNEL_TEXT_BASE (KERNBASE)
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freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
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/* Define a macro to simplify memory allocation */
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#define valloc_pages(var, np) \
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alloc_pages((var).pv_va, (np)); \
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(var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
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#define alloc_pages(var, np) \
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(var) = freemempos; \
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freemempos += (np * PAGE_SIZE); \
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memset((char *)(var), 0, ((np) * PAGE_SIZE));
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while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
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freemempos += PAGE_SIZE;
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valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
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valloc_pages(kernel_pt_table[loop],
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L2_TABLE_SIZE / PAGE_SIZE);
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} else {
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kernel_pt_table[loop].pv_va = freemempos -
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(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
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L2_TABLE_SIZE_REAL;
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kernel_pt_table[loop].pv_pa =
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kernel_pt_table[loop].pv_va - KERNVIRTADDR +
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KERNPHYSADDR;
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}
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i++;
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}
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/*
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* Allocate a page for the system page mapped to V0x00000000
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* This page will just contain the system vectors and can be
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* shared by all processes.
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*/
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valloc_pages(systempage, 1);
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/* Allocate stacks for all modes */
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valloc_pages(irqstack, IRQ_STACK_SIZE);
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valloc_pages(abtstack, ABT_STACK_SIZE);
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valloc_pages(undstack, UND_STACK_SIZE);
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valloc_pages(kernelstack, KSTACK_PAGES);
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alloc_pages(minidataclean.pv_pa, 1);
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valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
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/*
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* Now we start construction of the L1 page table
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* We start by mapping the L2 page tables into the L1.
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* This means that we can replace L1 mappings later on if necessary
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*/
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l1pagetable = kernel_l1pt.pv_va;
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/* Map the L2 pages tables in the L1 page table */
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pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
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&kernel_pt_table[KERNEL_PT_SYS]);
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for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
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pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x100000,
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&kernel_pt_table[KERNEL_PT_KERN + i]);
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pmap_map_chunk(l1pagetable, KERNBASE, KERNPHYSADDR,
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(((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
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- 1));
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for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
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pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
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&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
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}
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pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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/* Map the vector page. */
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pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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/* Map the stack pages */
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pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
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IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
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ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
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UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
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KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
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L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
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MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
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kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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}
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pmap_devmap_bootstrap(l1pagetable, kb920x_devmap);
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cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
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setttb(kernel_l1pt.pv_pa);
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cpu_tlb_flushID();
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cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
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cninit();
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memsize = board_init();
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physmem = memsize / PAGE_SIZE;
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/*
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* Pages were allocated during the secondary bootstrap for the
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* stacks for different CPU modes.
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* We must now set the r13 registers in the different CPU modes to
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* point to these stacks.
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* Since the ARM stacks use STMFD etc. we must set r13 to the top end
|
|
* of the stack memory.
|
|
*/
|
|
|
|
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
|
|
set_stackptr(PSR_IRQ32_MODE,
|
|
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
|
|
set_stackptr(PSR_ABT32_MODE,
|
|
abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
|
|
set_stackptr(PSR_UND32_MODE,
|
|
undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
|
|
|
|
|
|
|
|
/*
|
|
* We must now clean the cache again....
|
|
* Cleaning may be done by reading new data to displace any
|
|
* dirty data in the cache. This will have happened in setttb()
|
|
* but since we are boot strapping the addresses used for the read
|
|
* may have just been remapped and thus the cache could be out
|
|
* of sync. A re-clean after the switch will cure this.
|
|
* After booting there are no gross reloations of the kernel thus
|
|
* this problem will not occur after initarm().
|
|
*/
|
|
cpu_idcache_wbinv_all();
|
|
|
|
/* Set stack for exception handlers */
|
|
|
|
data_abort_handler_address = (u_int)data_abort_handler;
|
|
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
|
|
undefined_handler_address = (u_int)undefinedinstruction_bounce;
|
|
undefined_init();
|
|
|
|
proc_linkup(&proc0, &thread0);
|
|
thread0.td_kstack = kernelstack.pv_va;
|
|
thread0.td_pcb = (struct pcb *)
|
|
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
|
|
thread0.td_pcb->pcb_flags = 0;
|
|
thread0.td_frame = &proc0_tf;
|
|
pcpup->pc_curpcb = thread0.td_pcb;
|
|
|
|
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
|
|
|
|
pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1);
|
|
/*
|
|
* ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before
|
|
* calling pmap_bootstrap.
|
|
*/
|
|
dump_avail[0] = KERNPHYSADDR;
|
|
dump_avail[1] = KERNPHYSADDR + memsize;
|
|
dump_avail[2] = 0;
|
|
dump_avail[3] = 0;
|
|
|
|
pmap_bootstrap(freemempos,
|
|
KERNVIRTADDR + 3 * memsize,
|
|
&kernel_l1pt);
|
|
msgbufp = (void*)msgbufpv.pv_va;
|
|
msgbufinit(msgbufp, MSGBUF_SIZE);
|
|
mutex_init();
|
|
|
|
i = 0;
|
|
|
|
phys_avail[0] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
|
|
phys_avail[1] = KERNPHYSADDR + memsize;
|
|
phys_avail[2] = 0;
|
|
phys_avail[3] = 0;
|
|
/* Do basic tuning, hz etc */
|
|
init_param1();
|
|
init_param2(physmem);
|
|
kdb_init();
|
|
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
|
|
sizeof(struct pcb)));
|
|
}
|