718cf2ccb9
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387 lines
10 KiB
C
387 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013 Luiz Otavio O Souza.
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* Copyright (c) 2011-2012 Stefan Bethke.
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* Copyright (c) 2012 Adrian Chadd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/lock.h>
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#include <sys/kernel.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <dev/mii/mii.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/arswitch/arswitchreg.h>
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#include <dev/etherswitch/arswitch/arswitchvar.h>
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#include <dev/etherswitch/arswitch/arswitch_reg.h>
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#include <dev/etherswitch/arswitch/arswitch_vlans.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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/*
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* XXX TODO: teach about the AR934x SoC switch
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*/
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static int
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ar8xxx_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid,
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uint32_t data)
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{
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int err;
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if (arswitch_waitreg(sc->sc_dev, AR8X16_REG_VLAN_CTRL,
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AR8X16_VLAN_ACTIVE, 0, 5))
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return (EBUSY);
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/* Load the vlan data if needed. */
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if (op == AR8X16_VLAN_OP_LOAD) {
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err = arswitch_writereg(sc->sc_dev, AR8X16_REG_VLAN_DATA,
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(data & AR8X16_VLAN_MEMBER) | AR8X16_VLAN_VALID);
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if (err)
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return (err);
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}
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if (vid != 0)
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op |= ((vid & ETHERSWITCH_VID_MASK) << AR8X16_VLAN_VID_SHIFT);
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op |= AR8X16_VLAN_ACTIVE;
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arswitch_writereg(sc->sc_dev, AR8X16_REG_VLAN_CTRL, op);
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/* Wait for command processing. */
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if (arswitch_waitreg(sc->sc_dev, AR8X16_REG_VLAN_CTRL,
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AR8X16_VLAN_ACTIVE, 0, 5))
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return (EBUSY);
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return (0);
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}
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int
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ar8xxx_flush_dot1q_vlan(struct arswitch_softc *sc)
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{
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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return (ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_FLUSH, 0, 0));
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}
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int
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ar8xxx_purge_dot1q_vlan(struct arswitch_softc *sc, int vid)
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{
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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return (ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_PURGE, vid, 0));
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}
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int
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ar8xxx_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports,
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uint32_t *untagged_ports, int vid)
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{
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uint32_t reg;
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int err;
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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err = ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_GET, vid, 0);
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if (err)
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return (err);
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reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_VLAN_DATA);
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if ((reg & AR8X16_VLAN_VALID) == 0) {
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*ports = 0;
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return (EINVAL);
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}
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reg &= ((1 << (sc->numphys + 1)) - 1);
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*ports = reg;
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*untagged_ports = reg;
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return (0);
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}
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int
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ar8xxx_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports,
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uint32_t untagged_ports, int vid)
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{
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int err;
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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err = ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_LOAD, vid, ports);
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if (err)
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return (err);
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return (0);
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}
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int
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ar8xxx_get_port_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
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{
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int port;
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uint32_t reg;
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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/* For port based vlans the vlanid is the same as the port index. */
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port = vid & ETHERSWITCH_VID_MASK;
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reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port));
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*ports = (reg >> AR8X16_PORT_VLAN_DEST_PORTS_SHIFT);
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*ports &= AR8X16_VLAN_MEMBER;
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return (0);
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}
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int
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ar8xxx_set_port_vlan(struct arswitch_softc *sc, uint32_t ports, int vid)
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{
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int err, port;
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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/* For port based vlans the vlanid is the same as the port index. */
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port = vid & ETHERSWITCH_VID_MASK;
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err = arswitch_modifyreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port),
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AR8X16_VLAN_MEMBER << AR8X16_PORT_VLAN_DEST_PORTS_SHIFT,
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(ports & AR8X16_VLAN_MEMBER) << AR8X16_PORT_VLAN_DEST_PORTS_SHIFT);
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if (err)
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return (err);
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return (0);
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}
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/*
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* Reset vlans to default state.
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*/
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void
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ar8xxx_reset_vlans(struct arswitch_softc *sc)
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{
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uint32_t ports;
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int i, j;
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ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
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ARSWITCH_LOCK(sc);
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/* Reset all vlan data. */
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memset(sc->vid, 0, sizeof(sc->vid));
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/* Disable the QinQ and egress filters for all ports. */
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for (i = 0; i <= sc->numphys; i++) {
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if (arswitch_modifyreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(i),
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0x3 << AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT |
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AR8X16_PORT_CTRL_DOUBLE_TAG, 0)) {
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ARSWITCH_UNLOCK(sc);
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return;
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}
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}
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if (sc->hal.arswitch_flush_dot1q_vlan(sc)) {
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ARSWITCH_UNLOCK(sc);
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return;
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}
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if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
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/*
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* Reset the port based vlan settings and turn on the
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* ingress filter for all ports.
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*/
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ports = 0;
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for (i = 0; i <= sc->numphys; i++)
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arswitch_modifyreg(sc->sc_dev,
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AR8X16_REG_PORT_VLAN(i),
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AR8X16_PORT_VLAN_MODE_MASK |
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AR8X16_VLAN_MEMBER <<
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AR8X16_PORT_VLAN_DEST_PORTS_SHIFT,
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AR8X16_PORT_VLAN_MODE_SECURE <<
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AR8X16_PORT_VLAN_MODE_SHIFT);
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/*
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* Setup vlan 1 as PVID for all switch ports. Add all ports
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* as members of vlan 1.
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*/
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sc->vid[0] = 1;
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/* Set PVID for everyone. */
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for (i = 0; i <= sc->numphys; i++)
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sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]);
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ports = 0;
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for (i = 0; i <= sc->numphys; i++)
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ports |= (1 << i);
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sc->hal.arswitch_set_dot1q_vlan(sc, ports, sc->vid[0], sc->vid[0]);
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sc->vid[0] |= ETHERSWITCH_VID_VALID;
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} else if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {
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/* Initialize the port based vlans. */
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for (i = 0; i <= sc->numphys; i++) {
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sc->vid[i] = i | ETHERSWITCH_VID_VALID;
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ports = 0;
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for (j = 0; j <= sc->numphys; j++)
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ports |= (1 << j);
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arswitch_modifyreg(sc->sc_dev,
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AR8X16_REG_PORT_VLAN(i),
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AR8X16_PORT_VLAN_MODE_MASK |
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AR8X16_VLAN_MEMBER <<
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AR8X16_PORT_VLAN_DEST_PORTS_SHIFT,
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ports << AR8X16_PORT_VLAN_DEST_PORTS_SHIFT |
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AR8X16_PORT_VLAN_MODE_SECURE <<
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AR8X16_PORT_VLAN_MODE_PORT_ONLY);
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/* XXX TODO: SECURE / PORT_ONLY is wrong? */
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}
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} else {
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/* Disable the ingress filter and get everyone on all vlans. */
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for (i = 0; i <= sc->numphys; i++)
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arswitch_modifyreg(sc->sc_dev,
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AR8X16_REG_PORT_VLAN(i),
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AR8X16_PORT_VLAN_MODE_MASK |
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AR8X16_VLAN_MEMBER <<
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AR8X16_PORT_VLAN_DEST_PORTS_SHIFT,
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AR8X16_VLAN_MEMBER <<
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AR8X16_PORT_VLAN_DEST_PORTS_SHIFT |
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AR8X16_PORT_VLAN_MODE_SECURE <<
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AR8X16_PORT_VLAN_MODE_PORT_ONLY);
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}
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ARSWITCH_UNLOCK(sc);
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}
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int
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ar8xxx_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
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{
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int err;
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ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
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if (vg->es_vlangroup > sc->info.es_nvlangroups)
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return (EINVAL);
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/* Reset the members ports. */
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vg->es_untagged_ports = 0;
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vg->es_member_ports = 0;
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/* Not supported. */
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vg->es_fid = 0;
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/* Vlan ID. */
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ARSWITCH_LOCK(sc);
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vg->es_vid = sc->vid[vg->es_vlangroup];
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if ((vg->es_vid & ETHERSWITCH_VID_VALID) == 0) {
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ARSWITCH_UNLOCK(sc);
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return (0);
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}
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/* Member Ports. */
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switch (sc->vlan_mode) {
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case ETHERSWITCH_VLAN_DOT1Q:
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err = sc->hal.arswitch_get_dot1q_vlan(sc, &vg->es_member_ports,
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&vg->es_untagged_ports,
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vg->es_vid);
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break;
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case ETHERSWITCH_VLAN_PORT:
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err = sc->hal.arswitch_get_port_vlan(sc, &vg->es_member_ports,
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vg->es_vid);
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vg->es_untagged_ports = vg->es_member_ports;
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break;
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default:
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vg->es_member_ports = 0;
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vg->es_untagged_ports = 0;
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err = -1;
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}
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ARSWITCH_UNLOCK(sc);
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return (err);
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}
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int
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ar8xxx_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
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{
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int err, vid;
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ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
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/* Check VLAN mode. */
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if (sc->vlan_mode == 0)
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return (EINVAL);
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/*
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* Check if we are changing the vlanid for an already used vtu entry.
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* Then purge the entry first.
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*/
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ARSWITCH_LOCK(sc);
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vid = sc->vid[vg->es_vlangroup];
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if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q &&
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(vid & ETHERSWITCH_VID_VALID) != 0 &&
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(vid & ETHERSWITCH_VID_MASK) !=
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(vg->es_vid & ETHERSWITCH_VID_MASK)) {
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err = sc->hal.arswitch_purge_dot1q_vlan(sc, vid);
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if (err) {
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ARSWITCH_UNLOCK(sc);
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return (err);
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}
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}
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/* Vlan ID. */
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if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
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sc->vid[vg->es_vlangroup] = vg->es_vid & ETHERSWITCH_VID_MASK;
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/* Setting the vlanid to zero disables the vlangroup. */
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if (sc->vid[vg->es_vlangroup] == 0) {
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ARSWITCH_UNLOCK(sc);
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return (0);
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}
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sc->vid[vg->es_vlangroup] |= ETHERSWITCH_VID_VALID;
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vid = sc->vid[vg->es_vlangroup];
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}
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/* Member Ports. */
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switch (sc->vlan_mode) {
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case ETHERSWITCH_VLAN_DOT1Q:
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err = sc->hal.arswitch_set_dot1q_vlan(sc, vg->es_member_ports,
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vg->es_untagged_ports, vid);
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break;
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case ETHERSWITCH_VLAN_PORT:
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err = sc->hal.arswitch_set_port_vlan(sc, vg->es_member_ports, vid);
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break;
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default:
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err = -1;
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}
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ARSWITCH_UNLOCK(sc);
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return (err);
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}
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int
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ar8xxx_get_pvid(struct arswitch_softc *sc, int port, int *pvid)
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{
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uint32_t reg;
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port));
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*pvid = reg & 0xfff;
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return (0);
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}
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int
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ar8xxx_set_pvid(struct arswitch_softc *sc, int port, int pvid)
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{
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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return (arswitch_modifyreg(sc->sc_dev,
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AR8X16_REG_PORT_VLAN(port), 0xfff, pvid));
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}
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