633 lines
24 KiB
C
633 lines
24 KiB
C
/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @defgroup group_udma_interrupts UDMA I/O Fabric Interrupt Controller
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* @ingroup group_udma_api
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* UDMA IOFIC API
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* @{
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* @file al_hal_udma_iofic.h
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*
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* @brief C Header file for programming the interrupt controller that found
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* in UDMA based units. These APIs rely and use some the Interrupt controller
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* API under al_hal_iofic.h
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*/
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#ifndef __AL_HAL_UDMA_IOFIC_H__
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#define __AL_HAL_UDMA_IOFIC_H__
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#include <al_hal_common.h>
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#include <al_hal_iofic.h>
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#include <al_hal_udma_regs.h>
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/**
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* Interrupt Mode
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* This is the interrupt mode for the primary interrupt level The secondary
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* interrupt level does not have mode and it is always a level sensitive
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* interrupt that is reflected in group D of the primary.
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*/
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enum al_iofic_mode {
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AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
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AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
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AL_IOFIC_MODE_MSIX_PER_GROUP
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};
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/** interrupt controller level (primary/secondary) */
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enum al_udma_iofic_level {
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AL_UDMA_IOFIC_LEVEL_PRIMARY,
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AL_UDMA_IOFIC_LEVEL_SECONDARY
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};
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/*
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* The next four groups represents the standard 4 groups in the primary
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* interrupt controller of each bus-master unit in the I/O Fabric.
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* The first two groups can be used when accessing the secondary interrupt
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* controller as well.
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*/
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#define AL_INT_GROUP_A 0 /**< summary of the below events */
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#define AL_INT_GROUP_B 1 /**< RX completion queues */
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#define AL_INT_GROUP_C 2 /**< TX completion queues */
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#define AL_INT_GROUP_D 3 /**< Misc */
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/*******************************************************************************
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* Primary interrupt controller, group A bits
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******************************************************************************/
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/* Group A bits which are just summary bits of GROUP B, C and D */
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#define AL_INT_GROUP_A_GROUP_B_SUM AL_BIT(0)
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#define AL_INT_GROUP_A_GROUP_C_SUM AL_BIT(1)
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#define AL_INT_GROUP_A_GROUP_D_SUM AL_BIT(2)
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/*******************************************************************************
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* MSIX entry indices
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******************************************************************************/
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/** MSIX entry index for summary of group D in group A */
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#define AL_INT_MSIX_GROUP_A_SUM_D_IDX 2
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/** MSIX entry index for RX completion queue 0 */
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#define AL_INT_MSIX_RX_COMPLETION_START 3
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/*******************************************************************************
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* Primary interrupt controller, group D bits
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******************************************************************************/
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#define AL_INT_GROUP_D_CROSS_MAIL_BOXES \
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(AL_BIT(0) | AL_BIT(1) | AL_BIT(2) | AL_BIT(3))
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/** Summary of secondary interrupt controller, group A) */
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#define AL_INT_GROUP_D_M2S AL_BIT(8)
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/** Summary of secondary interrupt controller, group B) */
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#define AL_INT_GROUP_D_S2M AL_BIT(9)
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#define AL_INT_GROUP_D_SW_TIMER_INT AL_BIT(10)
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#define AL_INT_GROUP_D_APP_EXT_INT AL_BIT(11)
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#define AL_INT_GROUP_D_ALL \
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AL_INT_GROUP_D_CROSS_MAIL_BOXES | \
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AL_INT_GROUP_D_M2S | \
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AL_INT_GROUP_D_S2M | \
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AL_INT_GROUP_D_SW_TIMER_INT | \
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AL_INT_GROUP_D_APP_EXT_INT
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/*
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* Until this point, all description above is for Groups A/B/C/D in the PRIMARY
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* Interrupt controller.
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* Following are definitions related to the secondary interrupt controller with
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* two cause registers (group A and group B) that covers UDMA M2S/S2M errors.
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* Secondary interrupt controller summary bits are not mapped to the Processor
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* GIC directly, rather they are represented in Group D of the primary interrupt
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* controller.
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*/
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/******************************************************************************
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* Secondary interrupt Controller, Group A, which holds the TX (M2S) error
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* interrupt bits
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******************************************************************************/
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/**
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* MSIx response
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* MSIX Bus generator response error, the Bus response received with error indication
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*/
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#define AL_INT_2ND_GROUP_A_M2S_MSIX_RESP AL_BIT(27)
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/**
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* MSIx timeout MSIX Bus generator timeout error.
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* The generator didn't receive bus response for the MSIx write transaction.
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*/
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#define AL_INT_2ND_GROUP_A_M2S_MSIX_TO AL_BIT(26)
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/** Prefetch header buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_HDR_PARITY AL_BIT(25)
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/** Prefetch descriptor buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_DESC_PARITY AL_BIT(24)
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/** Data buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_DATA_PARITY AL_BIT(23)
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/** Data header buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_HDR_PARITY AL_BIT(22)
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/** Completion coalescing buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_COMPL_COAL_PARITY AL_BIT(21)
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/** UNACK packets buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_UNACK_PKT_PARITY AL_BIT(20)
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/** ACK packets buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_ACK_PKT_PARITY AL_BIT(19)
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/** AXI data buffer parity error */
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#define AL_INT_2ND_GROUP_A_M2S_AX_DATA_PARITY AL_BIT(18)
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/**
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* Prefetch Ring ID error
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* A wrong RingId was received while prefetching submission descriptor. This
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* could indicate a software bug or hardware failure, unless the UDMA is
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* working in a mode to ignore RingId (the al_udma_iofic_config() API can be
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* used to configure the UDMA to ignore the Ring ID check)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_RING_ID AL_BIT(17)
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/**
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* Prefetch last
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* Error in last bit indication of the descriptor
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* Descriptor with Last bit asserted is read from the queue to the prefetch
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* FIFO when the prefetch engine is not in a middle of packet processing (a
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* descriptor with First bit asserted should be read first to indicate start of
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* packet)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_LAST AL_BIT(16)
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/**
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* Prefetch first
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* Error in first bit indication of the descriptor
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* Descriptor with First bit asserted is read from the queue to the prefetch
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* FIFO while the prefetch engine is in a middle of packet processing ( a
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* descriptor with Last bit asserted should be read to indicate end of packet
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* before starting a new one)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_FIRST AL_BIT(15)
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/**
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* Prefetch max descriptors
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* Number of descriptors per packet exceeds the configurable maximum
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* descriptors per packet. This could indicate a software bug or a hardware
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* failure. (The al_udma_m2s_max_descs_set() API is used to configure the
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* maximum descriptors per packet)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_MAX_DESC AL_BIT(14)
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/**
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* Packet length
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* Packet length exceeds the configurable maximum packet size. The
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* al_udma_m2s_packet_size_cfg_set() API is used to configure the maximum
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* packet size)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PKT_LEN AL_BIT(13)
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/**
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* Prefetch AXI timeout
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* Bus request to I/O Fabric timeout error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_TO AL_BIT(12)
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/**
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* Prefetch AXI response
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* Bus response from I/O Fabric error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_RESP AL_BIT(11)
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/**
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* Prefetch AXI parity
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* Bus parity error on descriptor being prefetched
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*/
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#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_PARITY AL_BIT(10)
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/**
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* Data AXI timeout
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* Bus request to I/O Fabric timeout error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_TO AL_BIT(9)
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/**
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* Data AXI response
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* Bus response from I/O Fabric error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_RESP AL_BIT(8)
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/**
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* Data AXI parity
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* Bus parity error on data being read
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*/
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#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_PARITY AL_BIT(7)
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/**
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* Completion AXI timeout
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* Bus request to I/O Fabric timeout error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_CONPL_AXI_TO AL_BIT(6)
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/**
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* Completion AXI response
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* Bus response from I/O Fabric error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_COMPL_AXI_RESP AL_BIT(5)
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/**
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* Completion AXI parity
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* Bus generator internal SRAM parity error
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*/
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#define AL_INT_2ND_GROUP_A_M2S_COMP_AXI_PARITY AL_BIT(4)
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/**
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* Stream timeout
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* Application stream interface timeout indicating a failure at the Application
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* layer (RAID, Ethernet etc)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_STRM_TO AL_BIT(3)
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/**
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* Stream response
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* Application stream interface response error indicating a failure at the
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* Application layer (RAID, Ethernet etc)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_STRM_RESP AL_BIT(2)
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/**
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* Stream parity
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* Application stream interface parity error indicating a failure at the
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* Application layer (RAID, Ethernet etc)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_STRM_PARITY AL_BIT(1)
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/**
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* Stream completion mismatch
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* Application stream interface, packet serial mismatch error indicating a
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* failure at the Application layer (RAID, Ethernet etc)
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*/
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#define AL_INT_2ND_GROUP_A_M2S_STRM_COMPL_MISMATCH AL_BIT(0)
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/*******************************************************************************
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* Secondary interrupt Controller, Group B, which holds the RX (S2M) error
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* interrupt bits
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******************************************************************************/
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/** Prefetch descriptor buffer parity error */
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#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_DESC_PARITY AL_BIT(30)
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/** Completion coalescing buffer parity error */
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#define AL_INT_2ND_GROUP_B_S2M_COMPL_COAL_PARITY AL_BIT(29)
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/** PRE-UNACK packets buffer parity error */
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#define AL_INT_2ND_GROUP_B_S2M_PRE_UNACK_PKT_PARITY AL_BIT(28)
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/** UNACK packets buffer parity error */
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#define AL_INT_2ND_GROUP_B_S2M_UNACK_PKT_PARITY AL_BIT(27)
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/** Data buffer parity error */
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#define AL_INT_2ND_GROUP_B_S2M_DATA_PARITY AL_BIT(26)
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/** Data header buffer parity error */
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#define AL_INT_2ND_GROUP_B_S2M_DATA_HDR_PARITY AL_BIT(25)
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/**
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* Packet length
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* Application stream interface, Data counter length mismatch with metadata
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* packet length indicating a failure at the Application layer (RAID, Ethernet
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* etc)
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PKT_LEN AL_BIT(24)
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/**
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* Stream last
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* Application stream interface, error in Last bit indication, this error is
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* asserted when a 'last' indication is asserted on the stream interface
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* (between the application and the UDMA) when the interface is not in the
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* middle of packet, meaning that there was no 'first' indication before. This
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* indicates a failure at the application layer.
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*/
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#define AL_INT_2ND_GROUP_B_S2M_STRM_LAST AL_BIT(23)
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/**
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* Stream first
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* Application stream interface error in first bit indication, this error is
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* asserted when a 'first' indication is asserted on the stream interface
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* (between the application and the UDMA) when the interface is in the middle
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* of packet, meaning that there was a 'first' indication before and the UDMA
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* is waiting for a 'last' indication to end the packet. This indicates a
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* failure at the application layer.
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*/
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#define AL_INT_2ND_GROUP_B_S2M_STRM_FIRST AL_BIT(22)
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/**
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* Stream data
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* Application stream interface, error indication during data transaction
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*/
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#define AL_INT_2ND_GROUP_B_S2M_STRM_DATA AL_BIT(21)
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/**
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* Stream Data parity
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* Application stream interface, parity error during data transaction
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*/
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#define AL_INT_2ND_GROUP_B_S2M_STRM_DATA_PARITY AL_BIT(20)
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/**
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* Stream Header error
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* Application stream interface, error indication during header transaction
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*/
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#define AL_INT_2ND_GROUP_B_S2M_STRM_HDR AL_BIT(19)
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/**
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* Stream Header parity
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* Application stream interface, parity error during header transaction
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*/
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#define AL_INT_2ND_GROUP_B_S2M_STRM_HDR_PARITY AL_BIT(18)
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/**
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* Completion UNACK
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* Completion write, UNACK timeout due to completion FIFO back pressure
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*/
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#define AL_INT_2ND_GROUP_B_S2M_COMPL_UNACK AL_BIT(17)
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/**
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* Completion stream
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* Completion write, UNACK timeout due to stream ACK FIFO back pressure
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*/
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#define AL_INT_2ND_GROUP_B_S2M_COMPL_STRM AL_BIT(16)
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/**
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* Completion AXI timeout
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* Bus request to I/O Fabric timeout error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_TO AL_BIT(15)
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/**
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* Completion AXI response
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* Bus response from I/O Fabric error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_RESP AL_BIT(14)
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/**
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* Completion AXI parity
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* Completion Bus generator internal SRAM parity error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_PARITY AL_BIT(13)
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/**
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* Prefetch saturate
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* Prefetch engine, packet length counter saturated (32 bit) , this is caused
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* by an error at the application layer which sends packet data without
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* 'last'/'first' indication.
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_SAT AL_BIT(12)
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/**
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* Prefetch ring ID
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* Prefetch engine, Ring ID is not matching the expected RingID. This could
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* indicate a software bug or hardware failure, unless the UDMA is working in a
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* mode to ignore RingId (the al_udma_iofic_config() API can be used to
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* configure the UDMA to ignore the Ring ID check)
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_RING_ID AL_BIT(11)
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/**
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* Prefetch AXI timeout
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* Bus request to I/O Fabric timeout error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_TO AL_BIT(10)
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/**
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* Prefetch AXI response
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* Bus response from I/O Fabric error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_RESP AL_BIT(9)
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/**
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* Prefetch AXI parity
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* Bus parity error on descriptor being prefetched
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_PARITY AL_BIT(8)
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/**
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* No descriptors hint
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* Data write, Hint to the SW that there are not enough descriptors in the
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* queue for the current received packet. This is considered a hint and not an
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* error, as it could be a normal situation in certain application. The S2M
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* UDMA behavior when it runs out of Rx Descriptor is controlled by driver
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* which can use this hint to add more descriptors to the Rx queue.
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*/
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#define AL_INT_2ND_GROUP_B_S2M_NO_DESC_HINT AL_BIT(7)
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/**
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* No descriptors timeout
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* Data write, Timeout indication when there are not enough descriptors for the
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* current packet and the timeout expires. The S2M UDMA behavior when it runs
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* out of Rx Descriptor is controlled by driver which can use this hint to add
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* more descriptors to the Rx queue. The al_udma_s2m_no_desc_cfg_set() is used
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* to configure theUDMA S2M timeout and behavior when there are no Rx
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* descriptors for the received packet.
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*/
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#define AL_INT_2ND_GROUP_B_S2M_NO_DESC_TO AL_BIT(6)
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/**
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* Promotion indication
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* Data write, the data write engine checks the queue number of the two packets
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* at the head of the data FIFO, the data write engine notify the prefetch
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* engine to promote these queue numbers in the prefetch scheduler to make sure
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* that these queue will have RX descriptors for these packets. This error
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* indicates that the prefetch promotion didn't work for the second packet in
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* the FIFO. This is an indication used for system debug and not an error.
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*/
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#define AL_INT_2ND_GROUP_B_S2M_PROM_IND AL_BIT(5)
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/**
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* Header split ignored
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* Data write, The application requested header split but the buffer descriptor
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* doesn't include a second buffer for the header
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*/
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#define AL_INT_2ND_GROUP_B_S2M_HDR_SPLT_IGNORED AL_BIT(4)
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/**
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* Header split length
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* Data write, The application requested header split and the length of the
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* second buffer allocated for the header is not enough for the requested
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* header length. The remaining of the header is written to buffer 1 (data
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* buffer).
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*/
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#define AL_INT_2ND_GROUP_B_S2M_HDR_SPLT_LEN AL_BIT(3)
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/**
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* Data AXI timeout
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* Bus request to I/O Fabric timeout error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_TO AL_BIT(2)
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/**
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* Data AXI response
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* Bus response from I/O Fabric error
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*/
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#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_RESP AL_BIT(1)
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/**
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* Data AXI parity
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* Bus parity error on data being read
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*/
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#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_PARITY AL_BIT(0)
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/*******************************************************************************
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* Configurations
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******************************************************************************/
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/**
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* Configure the UDMA interrupt controller registers, interrupts will are kept
|
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* masked.
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* This is a static setting that should be called while initialized the
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* interrupt controller within a given UDMA, and should not be modified during
|
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* runtime unless the UDMA is completely disabled. The first argument sets the
|
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* interrupt and MSIX modes. The m2s/s2m errors/abort are a set of bit-wise
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* masks to define the behaviour of the UDMA once an error happens: The _abort
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* will put the UDMA in abort state once an error happens The _error bitmask
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* will indicate and error in the secondary cause register but will not abort.
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* The bit-mask that the _errors_disable and _aborts_disable are described in
|
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* 'AL_INT_2ND_GROUP_A_*' and 'AL_INT_2ND_GROUP_B_*'
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*
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* @param regs pointer to unit registers
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* @param mode interrupt scheme mode (legacy, MSI-X..)
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* @param m2s_errors_disable
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* This is a bit-wise mask, to indicate which one of the error causes in
|
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* secondary interrupt group_A should generate an interrupt. When a bit is
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* set, the error cause is ignored.
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* Recommended value: 0 (enable all errors).
|
|
* @param m2s_aborts_disable
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|
* This is a bit-wise mask, to indicate which one of the error causes in
|
|
* secondary interrupt group_A should automatically put the UDMA in
|
|
* abort state. When a bit is set, the error cause does cause an abort.
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|
* Recommended value: 0 (enable all aborts).
|
|
* @param s2m_errors_disable
|
|
* This is a bit-wise mask, to indicate which one of the error causes in
|
|
* secondary interrupt group_A should generate an interrupt. When a bit is
|
|
* set, the error cause is ignored.
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|
* Recommended value: 0xE0 (disable hint errors).
|
|
* @param s2m_aborts_disable
|
|
* This is a bit-wise mask, to indicate which one of the error causes in
|
|
* secondary interrupt group_A should automatically put the UDMA in
|
|
* abort state. When a bit is set, the error cause does cause an abort.
|
|
* Recommended value: 0xE0 (disable hint aborts).
|
|
*
|
|
* @return 0 on success. -EINVAL otherwise.
|
|
*/
|
|
int al_udma_iofic_config(struct unit_regs __iomem *regs,
|
|
enum al_iofic_mode mode,
|
|
uint32_t m2s_errors_disable,
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|
uint32_t m2s_aborts_disable,
|
|
uint32_t s2m_errors_disable,
|
|
uint32_t s2m_aborts_disable);
|
|
/**
|
|
* return the offset of the unmask register for a given group.
|
|
* this function can be used when the upper layer wants to directly
|
|
* access the unmask regiter and bypass the al_udma_iofic_unmask() API.
|
|
*
|
|
* @param regs pointer to udma registers
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
* @param group the interrupt group ('AL_INT_GROUP_*')
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|
* @return the offset of the unmask register.
|
|
*/
|
|
uint32_t __iomem * al_udma_iofic_unmask_offset_get(
|
|
struct unit_regs __iomem *regs,
|
|
enum al_udma_iofic_level level,
|
|
int group);
|
|
|
|
/**
|
|
* Get the interrupt controller base address for either the primary or secondary
|
|
* interrupt controller
|
|
*
|
|
* @param regs pointer to udma unit registers
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
*
|
|
* @returns The interrupt controller base address
|
|
*
|
|
*/
|
|
static INLINE void __iomem *al_udma_iofic_reg_base_get(
|
|
struct unit_regs __iomem *regs,
|
|
enum al_udma_iofic_level level)
|
|
{
|
|
void __iomem *iofic_regs = (level == AL_UDMA_IOFIC_LEVEL_PRIMARY) ?
|
|
(void __iomem *)®s->gen.interrupt_regs.main_iofic :
|
|
(void __iomem *)®s->gen.interrupt_regs.secondary_iofic_ctrl;
|
|
|
|
return iofic_regs;
|
|
}
|
|
|
|
/**
|
|
* Check the interrupt controller level/group validity
|
|
*
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
* @param group the interrupt group ('AL_INT_GROUP_*')
|
|
*
|
|
* @returns 0 - invalid, 1 - valid
|
|
*
|
|
*/
|
|
static INLINE int al_udma_iofic_level_and_group_valid(
|
|
enum al_udma_iofic_level level,
|
|
int group)
|
|
{
|
|
if (((level == AL_UDMA_IOFIC_LEVEL_PRIMARY) && (group >= 0) && (group < 4)) ||
|
|
((level == AL_UDMA_IOFIC_LEVEL_SECONDARY) && (group >= 0) && (group < 2)))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
/**
|
|
* unmask specific interrupts for a given group
|
|
* this functions uses the interrupt mask clear register to guarantee atomicity
|
|
* it's safe to call it while the mask is changed by the HW (auto mask) or another cpu.
|
|
*
|
|
* @param regs pointer to udma unit registers
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
* @param group the interrupt group ('AL_INT_GROUP_*')
|
|
* @param mask bitwise of interrupts to unmask, set bits will be unmasked.
|
|
*/
|
|
static INLINE void al_udma_iofic_unmask(
|
|
struct unit_regs __iomem *regs,
|
|
enum al_udma_iofic_level level,
|
|
int group,
|
|
uint32_t mask)
|
|
{
|
|
al_assert(al_udma_iofic_level_and_group_valid(level, group));
|
|
al_iofic_unmask(al_udma_iofic_reg_base_get(regs, level), group, mask);
|
|
}
|
|
|
|
/**
|
|
* mask specific interrupts for a given group
|
|
* this functions modifies interrupt mask register, the callee must make sure
|
|
* the mask is not changed by another cpu.
|
|
*
|
|
* @param regs pointer to udma unit registers
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
* @param group the interrupt group ('AL_INT_GROUP_*')
|
|
* @param mask bitwise of interrupts to mask, set bits will be masked.
|
|
*/
|
|
static INLINE void al_udma_iofic_mask(
|
|
struct unit_regs __iomem *regs,
|
|
enum al_udma_iofic_level level,
|
|
int group,
|
|
uint32_t mask)
|
|
{
|
|
al_assert(al_udma_iofic_level_and_group_valid(level, group));
|
|
al_iofic_mask(al_udma_iofic_reg_base_get(regs, level), group, mask);
|
|
}
|
|
|
|
/**
|
|
* read interrupt cause register for a given group
|
|
* this will clear the set bits if the Clear on Read mode enabled.
|
|
* @param regs pointer to udma unit registers
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
* @param group the interrupt group ('AL_INT_GROUP_*')
|
|
*/
|
|
static INLINE uint32_t al_udma_iofic_read_cause(
|
|
struct unit_regs __iomem *regs,
|
|
enum al_udma_iofic_level level,
|
|
int group)
|
|
{
|
|
al_assert(al_udma_iofic_level_and_group_valid(level, group));
|
|
return al_iofic_read_cause(al_udma_iofic_reg_base_get(regs, level), group);
|
|
}
|
|
|
|
/**
|
|
* clear bits in the interrupt cause register for a given group
|
|
*
|
|
* @param regs pointer to udma unit registers
|
|
* @param level the interrupt controller level (primary / secondary)
|
|
* @param group the interrupt group ('AL_INT_GROUP_*')
|
|
* @param mask bitwise of bits to be cleared, set bits will be cleared.
|
|
*/
|
|
static INLINE void al_udma_iofic_clear_cause(
|
|
struct unit_regs __iomem *regs,
|
|
enum al_udma_iofic_level level,
|
|
int group,
|
|
uint32_t mask)
|
|
{
|
|
al_assert(al_udma_iofic_level_and_group_valid(level, group));
|
|
al_iofic_clear_cause(al_udma_iofic_reg_base_get(regs, level), group, mask);
|
|
}
|
|
|
|
#endif
|
|
/** @} end of UDMA group */
|