e0b1369473
tree for two or more years now), except in a few places where there's code to be compatible with older versions of FreeBSD.
783 lines
20 KiB
C
783 lines
20 KiB
C
/*
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* Copyright (c) 2001-2003
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* Fraunhofer Institute for Open Communication Systems (FhG Fokus).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Hartmut Brandt <harti@freebsd.org>
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*
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* ForeHE driver.
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*
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* Transmission.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_inet.h"
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#include "opt_natm.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/conf.h>
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#include <sys/module.h>
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#include <sys/queue.h>
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#include <sys/syslog.h>
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#include <sys/condvar.h>
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#include <sys/sysctl.h>
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#include <vm/uma.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <net/if_atm.h>
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#include <net/route.h>
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#ifdef ENABLE_BPF
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#include <net/bpf.h>
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#endif
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#include <netinet/in.h>
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#include <netinet/if_atm.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/utopia/utopia.h>
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#include <dev/hatm/if_hatmconf.h>
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#include <dev/hatm/if_hatmreg.h>
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#include <dev/hatm/if_hatmvar.h>
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/*
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* Allocate a new TPD, zero the TPD part. Cannot return NULL if
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* flag is 0. The TPD is removed from the free list and its used
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* bit is set.
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*/
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static struct tpd *
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hatm_alloc_tpd(struct hatm_softc *sc, u_int flags)
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{
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struct tpd *t;
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/* if we allocate a transmit TPD check for the reserve */
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if (flags & M_NOWAIT) {
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if (sc->tpd_nfree <= HE_CONFIG_TPD_RESERVE)
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return (NULL);
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} else {
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if (sc->tpd_nfree == 0)
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return (NULL);
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}
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/* make it beeing used */
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t = SLIST_FIRST(&sc->tpd_free);
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KASSERT(t != NULL, ("tpd botch"));
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SLIST_REMOVE_HEAD(&sc->tpd_free, link);
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TPD_SET_USED(sc, t->no);
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sc->tpd_nfree--;
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/* initialize */
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t->mbuf = NULL;
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t->cid = 0;
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bzero(&t->tpd, sizeof(t->tpd));
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t->tpd.addr = t->no << HE_REGS_TPD_ADDR;
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return (t);
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}
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/*
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* Free a TPD. If the mbuf pointer in that TPD is not zero, it is assumed, that
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* the DMA map of this TPD was used to load this mbuf. The map is unloaded
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* and the mbuf is freed. The TPD is put back onto the free list and
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* its used bit is cleared.
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*/
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static void
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hatm_free_tpd(struct hatm_softc *sc, struct tpd *tpd)
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{
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if (tpd->mbuf != NULL) {
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bus_dmamap_unload(sc->tx_tag, tpd->map);
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m_freem(tpd->mbuf);
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tpd->mbuf = NULL;
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}
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/* insert TPD into free list */
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SLIST_INSERT_HEAD(&sc->tpd_free, tpd, link);
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TPD_CLR_USED(sc, tpd->no);
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sc->tpd_nfree++;
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}
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/*
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* Queue a number of TPD. If there is not enough space none of the TPDs
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* is queued and an error code is returned.
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*/
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static int
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hatm_queue_tpds(struct hatm_softc *sc, u_int count, struct tpd **list,
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u_int cid)
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{
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u_int space;
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u_int i;
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if (count >= sc->tpdrq.size) {
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sc->istats.tdprq_full++;
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return (EBUSY);
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}
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if (sc->tpdrq.tail < sc->tpdrq.head)
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space = sc->tpdrq.head - sc->tpdrq.tail;
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else
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space = sc->tpdrq.head - sc->tpdrq.tail + sc->tpdrq.size;
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if (space <= count) {
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sc->tpdrq.head =
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(READ4(sc, HE_REGO_TPDRQ_H) >> HE_REGS_TPDRQ_H_H) &
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(sc->tpdrq.size - 1);
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if (sc->tpdrq.tail < sc->tpdrq.head)
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space = sc->tpdrq.head - sc->tpdrq.tail;
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else
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space = sc->tpdrq.head - sc->tpdrq.tail +
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sc->tpdrq.size;
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if (space <= count) {
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if_printf(&sc->ifatm.ifnet, "TPDRQ full\n");
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sc->istats.tdprq_full++;
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return (EBUSY);
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}
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}
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/* we are going to write to the TPD queue space */
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bus_dmamap_sync(sc->tpdrq.mem.tag, sc->tpdrq.mem.map,
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BUS_DMASYNC_PREWRITE);
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/* put the entries into the TPD space */
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for (i = 0; i < count; i++) {
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/* we are going to 'write' the TPD to the device */
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bus_dmamap_sync(sc->tpds.tag, sc->tpds.map,
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BUS_DMASYNC_PREWRITE);
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sc->tpdrq.tpdrq[sc->tpdrq.tail].tpd =
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sc->tpds.paddr + HE_TPD_SIZE * list[i]->no;
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sc->tpdrq.tpdrq[sc->tpdrq.tail].cid = cid;
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if (++sc->tpdrq.tail == sc->tpdrq.size)
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sc->tpdrq.tail = 0;
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}
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/* update tail pointer */
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WRITE4(sc, HE_REGO_TPDRQ_T, (sc->tpdrq.tail << HE_REGS_TPDRQ_T_T));
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return (0);
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}
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/*
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* Helper struct for communication with the DMA load helper.
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*/
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struct load_txbuf_arg {
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struct hatm_softc *sc;
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struct tpd *first;
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struct mbuf *mbuf;
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struct hevcc *vcc;
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int error;
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u_int pti;
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u_int vpi, vci;
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};
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/*
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* Loader callback for the mbuf. This function allocates the TPDs and
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* fills them. It puts the dmamap and and the mbuf pointer into the last
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* TPD and then tries to queue all the TPDs. If anything fails, all TPDs
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* allocated by this function are freed and the error flag is set in the
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* argument structure. The first TPD must then be freed by the caller.
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*/
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static void
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hatm_load_txbuf(void *uarg, bus_dma_segment_t *segs, int nseg,
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bus_size_t mapsize, int error)
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{
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struct load_txbuf_arg *arg = uarg;
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u_int tpds_needed, i, n, tpd_cnt;
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int need_intr;
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struct tpd *tpd;
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struct tpd *tpd_list[HE_CONFIG_MAX_TPD_PER_PACKET];
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if (error != 0) {
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DBG(arg->sc, DMA, ("%s -- error=%d plen=%d\n",
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__func__, error, arg->mbuf->m_pkthdr.len));
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return;
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}
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/* ensure, we have enough TPDs (remember, we already have one) */
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tpds_needed = (nseg + 2) / 3;
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if (HE_CONFIG_TPD_RESERVE + tpds_needed - 1 > arg->sc->tpd_nfree) {
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if_printf(&arg->sc->ifatm.ifnet, "%s -- out of TPDs (need %d, "
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"have %u)\n", __func__, tpds_needed - 1,
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arg->sc->tpd_nfree + 1);
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arg->error = 1;
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return;
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}
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/*
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* Check for the maximum number of TPDs on the connection.
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*/
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need_intr = 0;
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if (arg->sc->max_tpd > 0) {
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if (arg->vcc->ntpds + tpds_needed > arg->sc->max_tpd) {
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arg->sc->istats.flow_closed++;
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arg->vcc->vflags |= HE_VCC_FLOW_CTRL;
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ATMEV_SEND_FLOW_CONTROL(&arg->sc->ifatm,
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arg->vpi, arg->vci, 1);
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arg->error = 1;
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return;
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}
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if (arg->vcc->ntpds + tpds_needed >
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(9 * arg->sc->max_tpd) / 10)
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need_intr = 1;
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}
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tpd = arg->first;
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tpd_cnt = 0;
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tpd_list[tpd_cnt++] = tpd;
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for (i = n = 0; i < nseg; i++, n++) {
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if (n == 3) {
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if ((tpd = hatm_alloc_tpd(arg->sc, M_NOWAIT)) == NULL)
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/* may not fail (see check above) */
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panic("%s: out of TPDs", __func__);
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tpd->cid = arg->first->cid;
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tpd->tpd.addr |= arg->pti;
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tpd_list[tpd_cnt++] = tpd;
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n = 0;
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}
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KASSERT(segs[i].ds_addr <= 0xffffffffLU,
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("phys addr too large %lx", (u_long)segs[i].ds_addr));
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DBG(arg->sc, DMA, ("DMA loaded: %lx/%lu",
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(u_long)segs[i].ds_addr, (u_long)segs[i].ds_len));
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tpd->tpd.bufs[n].addr = segs[i].ds_addr;
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tpd->tpd.bufs[n].len = segs[i].ds_len;
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DBG(arg->sc, TX, ("seg[%u]=tpd[%u,%u]=%x/%u", i,
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tpd_cnt, n, tpd->tpd.bufs[n].addr, tpd->tpd.bufs[n].len));
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if (i == nseg - 1)
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tpd->tpd.bufs[n].len |= HE_REGM_TPD_LST;
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}
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/*
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* Swap the MAP in the first and the last TPD and set the mbuf
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* pointer into the last TPD. We use the map in the last TPD, because
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* the map must stay valid until the last TPD is processed by the card.
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*/
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if (tpd_cnt > 1) {
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bus_dmamap_t tmp;
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tmp = arg->first->map;
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arg->first->map = tpd_list[tpd_cnt - 1]->map;
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tpd_list[tpd_cnt - 1]->map = tmp;
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}
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tpd_list[tpd_cnt - 1]->mbuf = arg->mbuf;
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if (need_intr)
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tpd_list[tpd_cnt - 1]->tpd.addr |= HE_REGM_TPD_INTR;
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/* queue the TPDs */
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if (hatm_queue_tpds(arg->sc, tpd_cnt, tpd_list, arg->first->cid)) {
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/* free all, except the first TPD */
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for (i = 1; i < tpd_cnt; i++)
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hatm_free_tpd(arg->sc, tpd_list[i]);
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arg->error = 1;
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return;
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}
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arg->vcc->ntpds += tpd_cnt;
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}
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/*
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* Start output on the interface
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*
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* For raw aal we process only the first cell in the mbuf chain! XXX
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*/
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void
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hatm_start(struct ifnet *ifp)
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{
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struct hatm_softc *sc = (struct hatm_softc *)ifp->if_softc;
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struct mbuf *m;
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struct atm_pseudohdr *aph;
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u_int cid;
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struct tpd *tpd;
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struct load_txbuf_arg arg;
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u_int len;
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int error;
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if (!(ifp->if_flags & IFF_RUNNING))
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return;
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mtx_lock(&sc->mtx);
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arg.sc = sc;
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while (1) {
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IF_DEQUEUE(&ifp->if_snd, m);
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if (m == NULL)
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break;
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if (m->m_len < sizeof(*aph))
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if ((m = m_pullup(m, sizeof(*aph))) == NULL)
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continue;
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aph = mtod(m, struct atm_pseudohdr *);
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arg.vci = ATM_PH_VCI(aph);
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arg.vpi = ATM_PH_VPI(aph);
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m_adj(m, sizeof(*aph));
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if ((len = m->m_pkthdr.len) == 0) {
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m_freem(m);
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continue;
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}
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if ((arg.vpi & ~HE_VPI_MASK) || (arg.vci & ~HE_VCI_MASK) ||
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(arg.vci == 0)) {
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m_freem(m);
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continue;
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}
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cid = HE_CID(arg.vpi, arg.vci);
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arg.vcc = sc->vccs[cid];
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if (arg.vcc == NULL || !(arg.vcc->vflags & HE_VCC_OPEN)) {
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m_freem(m);
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continue;
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}
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if (arg.vcc->vflags & HE_VCC_FLOW_CTRL) {
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m_freem(m);
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sc->istats.flow_drop++;
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continue;
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}
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arg.pti = 0;
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if (arg.vcc->param.aal == ATMIO_AAL_RAW) {
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if (len < 52) {
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m_freem(m);
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continue;
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}
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if (len > 52) {
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m_adj(m, -((int)(len - 52)));
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len = 52;
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}
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if (m->m_len < 4 && (m = m_pullup(m, 4)) == NULL)
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continue;
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/* ignore header except payload type and CLP */
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arg.pti = mtod(m, u_char *)[3] & 0xf;
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arg.pti = ((arg.pti & 0xe) << 2) | ((arg.pti & 1) << 1);
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m_adj(m, 4);
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len -= 4;
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}
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#ifdef ENABLE_BPF
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if (!(arg.vcc->param.flags & ATMIO_FLAG_NG) &&
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(arg.vcc->param.aal == ATMIO_AAL_5) &&
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(arg.vcc->param.flags & ATM_PH_LLCSNAP))
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BPF_MTAP(ifp, m);
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#endif
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/* Now load a DMA map with the packet. Allocate the first
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* TPD to get a map. Additional TPDs may be allocated by the
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* callback. */
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if ((tpd = hatm_alloc_tpd(sc, M_NOWAIT)) == NULL) {
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m_freem(m);
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sc->ifatm.ifnet.if_oerrors++;
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continue;
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}
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tpd->cid = cid;
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tpd->tpd.addr |= arg.pti;
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arg.first = tpd;
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arg.error = 0;
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arg.mbuf = m;
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error = bus_dmamap_load_mbuf(sc->tx_tag, tpd->map, m,
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hatm_load_txbuf, &arg, BUS_DMA_NOWAIT);
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if (error == EFBIG) {
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/* try to defragment the packet */
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sc->istats.defrag++;
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m = m_defrag(m, M_DONTWAIT);
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if (m == NULL) {
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sc->ifatm.ifnet.if_oerrors++;
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continue;
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}
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arg.mbuf = m;
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error = bus_dmamap_load_mbuf(sc->tx_tag, tpd->map, m,
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hatm_load_txbuf, &arg, BUS_DMA_NOWAIT);
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}
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if (error != 0) {
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if_printf(&sc->ifatm.ifnet, "mbuf loaded error=%d\n",
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error);
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hatm_free_tpd(sc, tpd);
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sc->ifatm.ifnet.if_oerrors++;
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continue;
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}
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if (arg.error) {
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hatm_free_tpd(sc, tpd);
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sc->ifatm.ifnet.if_oerrors++;
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continue;
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}
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arg.vcc->opackets++;
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arg.vcc->obytes += len;
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sc->ifatm.ifnet.if_opackets++;
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}
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mtx_unlock(&sc->mtx);
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}
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void
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hatm_tx_complete(struct hatm_softc *sc, struct tpd *tpd, uint32_t flags)
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{
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struct hevcc *vcc = sc->vccs[tpd->cid];
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DBG(sc, TX, ("tx_complete cid=%#x flags=%#x", tpd->cid, flags));
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if (vcc == NULL)
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return;
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if ((flags & HE_REGM_TBRQ_EOS) && (vcc->vflags & HE_VCC_TX_CLOSING)) {
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vcc->vflags &= ~HE_VCC_TX_CLOSING;
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if (vcc->param.flags & ATMIO_FLAG_ASYNC) {
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hatm_tx_vcc_closed(sc, tpd->cid);
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if (!(vcc->vflags & HE_VCC_OPEN)) {
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hatm_vcc_closed(sc, tpd->cid);
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vcc = NULL;
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}
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} else
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cv_signal(&sc->vcc_cv);
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}
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|
hatm_free_tpd(sc, tpd);
|
|
|
|
if (vcc == NULL)
|
|
return;
|
|
|
|
vcc->ntpds--;
|
|
|
|
if ((vcc->vflags & HE_VCC_FLOW_CTRL) &&
|
|
vcc->ntpds <= HE_CONFIG_TPD_FLOW_ENB) {
|
|
vcc->vflags &= ~HE_VCC_FLOW_CTRL;
|
|
ATMEV_SEND_FLOW_CONTROL(&sc->ifatm,
|
|
HE_VPI(tpd->cid), HE_VCI(tpd->cid), 0);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Convert CPS to Rate for a rate group
|
|
*/
|
|
static u_int
|
|
cps_to_rate(struct hatm_softc *sc, uint32_t cps)
|
|
{
|
|
u_int clk = sc->he622 ? HE_622_CLOCK : HE_155_CLOCK;
|
|
u_int period, rate;
|
|
|
|
/* how many double ticks between two cells */
|
|
period = (clk + 2 * cps - 1) / (2 * cps);
|
|
rate = hatm_cps2atmf(period);
|
|
if (hatm_atmf2cps(rate) < period)
|
|
rate++;
|
|
|
|
return (rate);
|
|
}
|
|
|
|
/*
|
|
* Check whether the VCC is really closed on the hardware and available for
|
|
* open. Check that we have enough resources. If this function returns ok,
|
|
* a later actual open must succeed. Assume, that we are locked between this
|
|
* function and the next one, so that nothing does change. For CBR this
|
|
* assigns the rate group and set the rate group's parameter.
|
|
*/
|
|
int
|
|
hatm_tx_vcc_can_open(struct hatm_softc *sc, u_int cid, struct hevcc *vcc)
|
|
{
|
|
uint32_t v, line_rate;
|
|
u_int rc, idx, free_idx;
|
|
struct atmio_tparam *t = &vcc->param.tparam;
|
|
|
|
/* verify that connection is closed */
|
|
#if 0
|
|
v = READ_TSR(sc, cid, 4);
|
|
if(!(v & HE_REGM_TSR4_SESS_END)) {
|
|
if_printf(&sc->ifatm.ifnet, "cid=%#x not closed (TSR4)\n", cid);
|
|
return (EBUSY);
|
|
}
|
|
#endif
|
|
v = READ_TSR(sc, cid, 0);
|
|
if((v & HE_REGM_TSR0_CONN_STATE) != 0) {
|
|
if_printf(&sc->ifatm.ifnet, "cid=%#x not closed (TSR0=%#x)\n",
|
|
cid, v);
|
|
return (EBUSY);
|
|
}
|
|
|
|
/* check traffic parameters */
|
|
line_rate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M;
|
|
switch (vcc->param.traffic) {
|
|
|
|
case ATMIO_TRAFFIC_UBR:
|
|
if (t->pcr == 0 || t->pcr > line_rate)
|
|
t->pcr = line_rate;
|
|
if (t->mcr != 0 || t->icr != 0 || t->tbe != 0 || t->nrm != 0 ||
|
|
t->trm != 0 || t->adtf != 0 || t->rif != 0 || t->rdf != 0 ||
|
|
t->cdf != 0)
|
|
return (EINVAL);
|
|
break;
|
|
|
|
case ATMIO_TRAFFIC_CBR:
|
|
/*
|
|
* Compute rate group index
|
|
*/
|
|
if (t->pcr < 10)
|
|
t->pcr = 10;
|
|
if (sc->cbr_bw + t->pcr > line_rate)
|
|
return (EINVAL);
|
|
if (t->mcr != 0 || t->icr != 0 || t->tbe != 0 || t->nrm != 0 ||
|
|
t->trm != 0 || t->adtf != 0 || t->rif != 0 || t->rdf != 0 ||
|
|
t->cdf != 0)
|
|
return (EINVAL);
|
|
|
|
rc = cps_to_rate(sc, t->pcr);
|
|
free_idx = HE_REGN_CS_STPER;
|
|
for (idx = 0; idx < HE_REGN_CS_STPER; idx++) {
|
|
if (sc->rate_ctrl[idx].refcnt == 0) {
|
|
if (free_idx == HE_REGN_CS_STPER)
|
|
free_idx = idx;
|
|
} else {
|
|
if (sc->rate_ctrl[idx].rate == rc)
|
|
break;
|
|
}
|
|
}
|
|
if (idx == HE_REGN_CS_STPER) {
|
|
if ((idx = free_idx) == HE_REGN_CS_STPER)
|
|
return (EBUSY);
|
|
sc->rate_ctrl[idx].rate = rc;
|
|
}
|
|
vcc->rc = idx;
|
|
|
|
/* commit */
|
|
sc->rate_ctrl[idx].refcnt++;
|
|
sc->cbr_bw += t->pcr;
|
|
break;
|
|
|
|
case ATMIO_TRAFFIC_ABR:
|
|
if (t->pcr > line_rate)
|
|
t->pcr = line_rate;
|
|
if (t->mcr > line_rate)
|
|
t->mcr = line_rate;
|
|
if (t->icr > line_rate)
|
|
t->icr = line_rate;
|
|
if (t->tbe == 0 || t->tbe >= 1 << 24 || t->nrm > 7 ||
|
|
t->trm > 7 || t->adtf >= 1 << 10 || t->rif > 15 ||
|
|
t->rdf > 15 || t->cdf > 7)
|
|
return (EINVAL);
|
|
break;
|
|
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
#define NRM_CODE2VAL(CODE) (2 * (1 << (CODE)))
|
|
|
|
/*
|
|
* Actually open the transmit VCC
|
|
*/
|
|
void
|
|
hatm_tx_vcc_open(struct hatm_softc *sc, u_int cid)
|
|
{
|
|
struct hevcc *vcc = sc->vccs[cid];
|
|
uint32_t tsr0, tsr4, atmf, crm;
|
|
const struct atmio_tparam *t = &vcc->param.tparam;
|
|
|
|
if (vcc->param.aal == ATMIO_AAL_5) {
|
|
tsr0 = HE_REGM_TSR0_AAL_5 << HE_REGS_TSR0_AAL;
|
|
tsr4 = HE_REGM_TSR4_AAL_5 << HE_REGS_TSR4_AAL;
|
|
} else {
|
|
tsr0 = HE_REGM_TSR0_AAL_0 << HE_REGS_TSR0_AAL;
|
|
tsr4 = HE_REGM_TSR4_AAL_0 << HE_REGS_TSR4_AAL;
|
|
}
|
|
tsr4 |= 1;
|
|
|
|
switch (vcc->param.traffic) {
|
|
|
|
case ATMIO_TRAFFIC_UBR:
|
|
atmf = hatm_cps2atmf(t->pcr);
|
|
|
|
tsr0 |= HE_REGM_TSR0_TRAFFIC_UBR << HE_REGS_TSR0_TRAFFIC;
|
|
tsr0 |= HE_REGM_TSR0_USE_WMIN | HE_REGM_TSR0_UPDATE_GER;
|
|
|
|
WRITE_TSR(sc, cid, 0, 0xf, tsr0);
|
|
WRITE_TSR(sc, cid, 4, 0xf, tsr4);
|
|
WRITE_TSR(sc, cid, 1, 0xf, (atmf << HE_REGS_TSR1_PCR));
|
|
WRITE_TSR(sc, cid, 2, 0xf, (atmf << HE_REGS_TSR2_ACR));
|
|
WRITE_TSR(sc, cid, 9, 0xf, HE_REGM_TSR9_INIT);
|
|
WRITE_TSR(sc, cid, 3, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 5, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 6, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 7, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 8, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 10, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 11, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 12, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 13, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 14, 0xf, 0);
|
|
break;
|
|
|
|
case ATMIO_TRAFFIC_CBR:
|
|
atmf = hatm_cps2atmf(t->pcr);
|
|
|
|
if (sc->rate_ctrl[vcc->rc].refcnt == 1)
|
|
WRITE_MBOX4(sc, HE_REGO_CS_STPER(vcc->rc),
|
|
sc->rate_ctrl[vcc->rc].rate);
|
|
|
|
tsr0 |= HE_REGM_TSR0_TRAFFIC_CBR << HE_REGS_TSR0_TRAFFIC;
|
|
tsr0 |= vcc->rc;
|
|
|
|
WRITE_TSR(sc, cid, 1, 0xf, (atmf << HE_REGS_TSR1_PCR));
|
|
WRITE_TSR(sc, cid, 2, 0xf, (atmf << HE_REGS_TSR2_ACR));
|
|
WRITE_TSR(sc, cid, 3, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 5, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 6, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 7, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 8, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 10, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 11, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 12, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 13, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 14, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 4, 0xf, tsr4);
|
|
WRITE_TSR(sc, cid, 9, 0xf, HE_REGM_TSR9_INIT);
|
|
WRITE_TSR(sc, cid, 0, 0xf, tsr0);
|
|
|
|
break;
|
|
|
|
case ATMIO_TRAFFIC_ABR:
|
|
if ((crm = t->tbe / NRM_CODE2VAL(t->nrm)) > 0xffff)
|
|
crm = 0xffff;
|
|
|
|
tsr0 |= HE_REGM_TSR0_TRAFFIC_ABR << HE_REGS_TSR0_TRAFFIC;
|
|
tsr0 |= HE_REGM_TSR0_USE_WMIN | HE_REGM_TSR0_UPDATE_GER;
|
|
|
|
WRITE_TSR(sc, cid, 0, 0xf, tsr0);
|
|
WRITE_TSR(sc, cid, 4, 0xf, tsr4);
|
|
|
|
WRITE_TSR(sc, cid, 1, 0xf,
|
|
((hatm_cps2atmf(t->pcr) << HE_REGS_TSR1_PCR) |
|
|
(hatm_cps2atmf(t->mcr) << HE_REGS_TSR1_MCR)));
|
|
WRITE_TSR(sc, cid, 2, 0xf,
|
|
(hatm_cps2atmf(t->icr) << HE_REGS_TSR2_ACR));
|
|
WRITE_TSR(sc, cid, 3, 0xf,
|
|
((NRM_CODE2VAL(t->nrm) - 1) << HE_REGS_TSR3_NRM) |
|
|
(crm << HE_REGS_TSR3_CRM));
|
|
|
|
WRITE_TSR(sc, cid, 5, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 6, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 7, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 8, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 10, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 12, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 14, 0xf, 0);
|
|
WRITE_TSR(sc, cid, 9, 0xf, HE_REGM_TSR9_INIT);
|
|
|
|
WRITE_TSR(sc, cid, 11, 0xf,
|
|
(hatm_cps2atmf(t->icr) << HE_REGS_TSR11_ICR) |
|
|
(t->trm << HE_REGS_TSR11_TRM) |
|
|
(t->nrm << HE_REGS_TSR11_NRM) |
|
|
(t->adtf << HE_REGS_TSR11_ADTF));
|
|
|
|
WRITE_TSR(sc, cid, 13, 0xf,
|
|
(t->rdf << HE_REGS_TSR13_RDF) |
|
|
(t->rif << HE_REGS_TSR13_RIF) |
|
|
(t->cdf << HE_REGS_TSR13_CDF) |
|
|
(crm << HE_REGS_TSR13_CRM));
|
|
|
|
break;
|
|
|
|
default:
|
|
return;
|
|
}
|
|
|
|
vcc->vflags |= HE_VCC_TX_OPEN;
|
|
}
|
|
|
|
/*
|
|
* Close the TX side of a VCC. Set the CLOSING flag.
|
|
*/
|
|
void
|
|
hatm_tx_vcc_close(struct hatm_softc *sc, u_int cid)
|
|
{
|
|
struct hevcc *vcc = sc->vccs[cid];
|
|
struct tpd *tpd_list[1];
|
|
u_int i, pcr = 0;
|
|
|
|
WRITE_TSR(sc, cid, 4, 0x8, HE_REGM_TSR4_FLUSH);
|
|
|
|
switch (vcc->param.traffic) {
|
|
|
|
case ATMIO_TRAFFIC_CBR:
|
|
WRITE_TSR(sc, cid, 14, 0x8, HE_REGM_TSR14_CBR_DELETE);
|
|
break;
|
|
|
|
case ATMIO_TRAFFIC_ABR:
|
|
WRITE_TSR(sc, cid, 14, 0x4, HE_REGM_TSR14_ABR_CLOSE);
|
|
pcr = vcc->param.tparam.pcr;
|
|
/* FALL THROUGH */
|
|
|
|
case ATMIO_TRAFFIC_UBR:
|
|
WRITE_TSR(sc, cid, 1, 0xf,
|
|
hatm_cps2atmf(HE_CONFIG_FLUSH_RATE) << HE_REGS_TSR1_MCR |
|
|
hatm_cps2atmf(pcr) << HE_REGS_TSR1_PCR);
|
|
break;
|
|
}
|
|
|
|
tpd_list[0] = hatm_alloc_tpd(sc, 0);
|
|
tpd_list[0]->tpd.addr |= HE_REGM_TPD_EOS | HE_REGM_TPD_INTR;
|
|
tpd_list[0]->cid = cid;
|
|
|
|
vcc->vflags |= HE_VCC_TX_CLOSING;
|
|
vcc->vflags &= ~HE_VCC_TX_OPEN;
|
|
|
|
i = 0;
|
|
while (hatm_queue_tpds(sc, 1, tpd_list, cid) != 0) {
|
|
if (++i == 1000)
|
|
panic("TPDRQ permanently full");
|
|
DELAY(1000);
|
|
}
|
|
}
|
|
|
|
void
|
|
hatm_tx_vcc_closed(struct hatm_softc *sc, u_int cid)
|
|
{
|
|
if (sc->vccs[cid]->param.traffic == ATMIO_TRAFFIC_CBR) {
|
|
sc->cbr_bw -= sc->vccs[cid]->param.tparam.pcr;
|
|
sc->rate_ctrl[sc->vccs[cid]->rc].refcnt--;
|
|
}
|
|
}
|