3d4a180923
When the guest is bringing up the APs in the x2APIC mode a write to the ICR register will now trigger a return to userspace with an exitcode of VM_EXITCODE_SPINUP_AP. This gets SMP guests working again with x2APIC. Change the vlapic timer lock to be a spinlock because the vlapic can be accessed from within a critical section (vm run loop) when guest is using x2apic mode. Reviewed by: grehan@
88 lines
3.0 KiB
C
88 lines
3.0 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_LAPIC_H_
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#define _VMM_LAPIC_H_
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struct vm;
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boolean_t lapic_msr(u_int num);
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int lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval,
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bool *retu);
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int lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t wval,
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bool *retu);
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int lapic_mmio_read(void *vm, int cpu, uint64_t gpa,
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uint64_t *rval, int size, void *arg);
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int lapic_mmio_write(void *vm, int cpu, uint64_t gpa,
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uint64_t wval, int size, void *arg);
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/*
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* Returns a vector between 32 and 255 if an interrupt is pending in the
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* IRR that can be delivered based on the current state of ISR and TPR.
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*
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* Note that the vector does not automatically transition to the ISR as a
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* result of calling this function.
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*
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* Returns -1 if there is no eligible vector that can be delivered to the
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* guest at this time.
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*/
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int lapic_pending_intr(struct vm *vm, int cpu);
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/*
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* Transition 'vector' from IRR to ISR. This function is called with the
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* vector returned by 'lapic_pending_intr()' when the guest is able to
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* accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
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* block interrupt delivery).
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*/
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void lapic_intr_accepted(struct vm *vm, int cpu, int vector);
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/*
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* Signals to the LAPIC that an interrupt at 'vector' needs to be generated
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* to the 'cpu', the state is recorded in IRR.
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*/
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int lapic_set_intr(struct vm *vm, int cpu, int vector, bool trig);
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#define LAPIC_TRIG_LEVEL true
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#define LAPIC_TRIG_EDGE false
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static __inline int
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lapic_intr_level(struct vm *vm, int cpu, int vector)
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{
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return (lapic_set_intr(vm, cpu, vector, LAPIC_TRIG_LEVEL));
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}
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static __inline int
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lapic_intr_edge(struct vm *vm, int cpu, int vector)
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{
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return (lapic_set_intr(vm, cpu, vector, LAPIC_TRIG_EDGE));
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}
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#endif
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