George V. Neville-Neil 2e7de50933 Add counters for the i7 architecture which were accidentally left ... out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month		2009-09-01 17:55:37 +00:00
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hwpmc_amd.c
hwpmc_amd.h
hwpmc_arm.c
hwpmc_core.c	Add counters for the i7 architecture which were accidentally left	2009-09-01 17:55:37 +00:00
hwpmc_core.h
hwpmc_ia64.c
hwpmc_intel.c
hwpmc_logging.c
hwpmc_mod.c
hwpmc_pentium.c
hwpmc_pentium.h
hwpmc_piv.c	Adjust the handling of the local APIC PMC interrupt vector:	2009-08-14 21:05:08 +00:00
hwpmc_piv.h
hwpmc_powerpc.c
hwpmc_ppro.c	Adjust the handling of the local APIC PMC interrupt vector:	2009-08-14 21:05:08 +00:00
hwpmc_ppro.h
hwpmc_sparc64.c
hwpmc_tsc.c
hwpmc_tsc.h
hwpmc_x86.c	Adjust the handling of the local APIC PMC interrupt vector:	2009-08-14 21:05:08 +00:00
pmc_events.h	Add counters for the i7 architecture which were accidentally left	2009-09-01 17:55:37 +00:00