570 lines
13 KiB
C
570 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2011 Nathan Whitehorn
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/rtas.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#ifdef POWERNV
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#include <powerpc/powernv/opal.h>
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#endif
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#include "phyp-hvcall.h"
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#include "pic_if.h"
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#define XICP_PRIORITY 5 /* Random non-zero number */
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#define XICP_IPI 2
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#define MAX_XICP_IRQS (1<<24) /* 24-bit XIRR field */
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#define XIVE_XICS_MODE_EMU 0
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#define XIVE_XICS_MODE_EXP 1
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static int xicp_probe(device_t);
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static int xicp_attach(device_t);
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static int xics_probe(device_t);
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static int xics_attach(device_t);
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static void xicp_bind(device_t dev, u_int irq, cpuset_t cpumask);
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static void xicp_dispatch(device_t, struct trapframe *);
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static void xicp_enable(device_t, u_int, u_int);
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static void xicp_eoi(device_t, u_int);
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static void xicp_ipi(device_t, u_int);
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static void xicp_mask(device_t, u_int);
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static void xicp_unmask(device_t, u_int);
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#ifdef POWERNV
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void xicp_smp_cpu_startup(void);
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#endif
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static device_method_t xicp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, xicp_probe),
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DEVMETHOD(device_attach, xicp_attach),
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/* PIC interface */
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DEVMETHOD(pic_bind, xicp_bind),
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DEVMETHOD(pic_dispatch, xicp_dispatch),
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DEVMETHOD(pic_enable, xicp_enable),
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DEVMETHOD(pic_eoi, xicp_eoi),
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DEVMETHOD(pic_ipi, xicp_ipi),
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DEVMETHOD(pic_mask, xicp_mask),
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DEVMETHOD(pic_unmask, xicp_unmask),
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DEVMETHOD_END
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};
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static device_method_t xics_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, xics_probe),
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DEVMETHOD(device_attach, xics_attach),
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DEVMETHOD_END
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};
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struct xicp_softc {
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struct mtx sc_mtx;
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struct resource *mem[MAXCPU];
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int cpu_range[2];
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int ibm_int_on;
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int ibm_int_off;
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int ibm_get_xive;
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int ibm_set_xive;
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/* XXX: inefficient -- hash table? tree? */
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struct {
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int irq;
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int vector;
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int cpu;
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} intvecs[256];
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int nintvecs;
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bool xics_emu;
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};
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static driver_t xicp_driver = {
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"xicp",
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xicp_methods,
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sizeof(struct xicp_softc)
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};
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static driver_t xics_driver = {
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"xics",
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xics_methods,
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0
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};
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#ifdef POWERNV
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/* We can only pass physical addresses into OPAL. Kernel stacks are in the KVA,
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* not in the direct map, so we need to somehow extract the physical address.
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* However, pmap_kextract() takes locks, which is forbidden in a critical region
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* (which PIC_DISPATCH() operates in). The kernel is mapped into the Direct
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* Map (0xc000....), and the CPU implicitly drops the top two bits when doing
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* real address by nature that the bus width is smaller than 64-bits. Placing
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* cpu_xirr into the DMAP lets us take advantage of this and avoids the
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* pmap_kextract() that would otherwise be needed if using the stack variable.
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*/
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static uint32_t cpu_xirr[MAXCPU];
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#endif
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static devclass_t xicp_devclass;
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static devclass_t xics_devclass;
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EARLY_DRIVER_MODULE(xicp, ofwbus, xicp_driver, xicp_devclass, 0, 0,
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BUS_PASS_INTERRUPT-1);
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EARLY_DRIVER_MODULE(xics, ofwbus, xics_driver, xics_devclass, 0, 0,
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BUS_PASS_INTERRUPT);
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#ifdef POWERNV
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static struct resource *
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xicp_mem_for_cpu(int cpu)
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{
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device_t dev;
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struct xicp_softc *sc;
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int i;
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for (i = 0; (dev = devclass_get_device(xicp_devclass, i)) != NULL; i++){
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sc = device_get_softc(dev);
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if (cpu >= sc->cpu_range[0] && cpu < sc->cpu_range[1])
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return (sc->mem[cpu - sc->cpu_range[0]]);
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}
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return (NULL);
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}
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#endif
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static int
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xicp_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "ibm,ppc-xicp") &&
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!ofw_bus_is_compatible(dev, "ibm,opal-intc"))
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return (ENXIO);
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device_set_desc(dev, "External Interrupt Presentation Controller");
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return (BUS_PROBE_GENERIC);
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}
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static int
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xics_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "ibm,ppc-xics") &&
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!ofw_bus_is_compatible(dev, "IBM,opal-xics"))
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return (ENXIO);
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device_set_desc(dev, "External Interrupt Source Controller");
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return (BUS_PROBE_GENERIC);
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}
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static int
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xicp_attach(device_t dev)
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{
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struct xicp_softc *sc = device_get_softc(dev);
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phandle_t phandle = ofw_bus_get_node(dev);
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if (rtas_exists()) {
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sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
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sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
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sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
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sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
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#ifdef POWERNV
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} else if (opal_check() == 0) {
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/* No init needed */
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#endif
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} else {
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device_printf(dev, "Cannot attach without RTAS or OPAL\n");
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return (ENXIO);
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}
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if (OF_hasprop(phandle, "ibm,interrupt-server-ranges")) {
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OF_getencprop(phandle, "ibm,interrupt-server-ranges",
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sc->cpu_range, sizeof(sc->cpu_range));
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sc->cpu_range[1] += sc->cpu_range[0];
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device_printf(dev, "Handling CPUs %d-%d\n", sc->cpu_range[0],
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sc->cpu_range[1]-1);
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#ifdef POWERNV
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} else if (ofw_bus_is_compatible(dev, "ibm,opal-intc")) {
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/*
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* For now run POWER9 XIVE interrupt controller in XICS
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* compatibility mode.
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*/
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sc->xics_emu = true;
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opal_call(OPAL_XIVE_RESET, XIVE_XICS_MODE_EMU);
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#endif
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} else {
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sc->cpu_range[0] = 0;
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sc->cpu_range[1] = mp_ncpus;
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}
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#ifdef POWERNV
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if (mfmsr() & PSL_HV) {
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int i;
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if (sc->xics_emu) {
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opal_call(OPAL_INT_SET_CPPR, 0xff);
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for (i = 0; i < mp_ncpus; i++) {
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opal_call(OPAL_INT_SET_MFRR,
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pcpu_find(i)->pc_hwref, 0xff);
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}
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} else {
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for (i = 0; i < sc->cpu_range[1] - sc->cpu_range[0]; i++) {
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sc->mem[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&i, RF_ACTIVE);
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if (sc->mem[i] == NULL) {
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device_printf(dev, "Could not alloc mem "
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"resource %d\n", i);
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return (ENXIO);
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}
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/* Unmask interrupts on all cores */
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bus_write_1(sc->mem[i], 4, 0xff);
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bus_write_1(sc->mem[i], 12, 0xff);
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}
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}
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}
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#endif
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mtx_init(&sc->sc_mtx, "XICP", NULL, MTX_DEF);
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sc->nintvecs = 0;
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powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XICP_IRQS,
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1 /* Number of IPIs */, FALSE);
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root_pic = dev;
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return (0);
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}
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static int
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xics_attach(device_t dev)
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{
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phandle_t phandle = ofw_bus_get_node(dev);
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/* The XICP (root PIC) will handle all our interrupts */
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powerpc_register_pic(root_pic, OF_xref_from_node(phandle),
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MAX_XICP_IRQS, 1 /* Number of IPIs */, FALSE);
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return (0);
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}
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/*
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* PIC I/F methods.
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*/
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static void
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xicp_bind(device_t dev, u_int irq, cpuset_t cpumask)
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{
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struct xicp_softc *sc = device_get_softc(dev);
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cell_t status, cpu;
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int ncpus, i, error;
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/* Ignore IPIs */
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if (irq == MAX_XICP_IRQS)
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return;
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/*
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* This doesn't appear to actually support affinity groups, so pick a
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* random CPU.
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*/
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ncpus = 0;
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CPU_FOREACH(cpu)
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if (CPU_ISSET(cpu, &cpumask)) ncpus++;
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i = mftb() % ncpus;
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ncpus = 0;
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CPU_FOREACH(cpu) {
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if (!CPU_ISSET(cpu, &cpumask))
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continue;
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if (ncpus == i)
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break;
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ncpus++;
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}
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cpu = pcpu_find(cpu)->pc_hwref;
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/* XXX: super inefficient */
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for (i = 0; i < sc->nintvecs; i++) {
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if (sc->intvecs[i].irq == irq) {
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sc->intvecs[i].cpu = cpu;
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break;
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}
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}
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KASSERT(i < sc->nintvecs, ("Binding non-configured interrupt"));
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if (rtas_exists())
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error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
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XICP_PRIORITY, &status);
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#ifdef POWERNV
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else
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error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
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#endif
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if (error < 0)
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panic("Cannot bind interrupt %d to CPU %d", irq, cpu);
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}
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static void
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xicp_dispatch(device_t dev, struct trapframe *tf)
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{
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struct xicp_softc *sc;
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struct resource *regs = NULL;
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uint64_t xirr, junk;
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int i;
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sc = device_get_softc(dev);
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#ifdef POWERNV
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if ((mfmsr() & PSL_HV) && !sc->xics_emu) {
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regs = xicp_mem_for_cpu(PCPU_GET(hwref));
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KASSERT(regs != NULL,
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("Can't find regs for CPU %ld", (uintptr_t)PCPU_GET(hwref)));
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}
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#endif
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for (;;) {
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/* Return value in R4, use the PFT call */
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if (regs) {
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xirr = bus_read_4(regs, 4);
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#ifdef POWERNV
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} else if (sc->xics_emu) {
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opal_call(OPAL_INT_GET_XIRR, &cpu_xirr[PCPU_GET(cpuid)],
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false);
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xirr = cpu_xirr[PCPU_GET(cpuid)];
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#endif
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} else {
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/* Return value in R4, use the PFT call */
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phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
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}
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xirr &= 0x00ffffff;
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if (xirr == 0) /* No more pending interrupts? */
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break;
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if (xirr == XICP_IPI) { /* Magic number for IPIs */
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xirr = MAX_XICP_IRQS; /* Map to FreeBSD magic */
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/* Clear IPI */
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if (regs)
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bus_write_1(regs, 12, 0xff);
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#ifdef POWERNV
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else if (sc->xics_emu)
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opal_call(OPAL_INT_SET_MFRR,
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PCPU_GET(hwref), 0xff);
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#endif
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else
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phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(hwref)),
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0xff);
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}
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/* XXX: super inefficient */
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for (i = 0; i < sc->nintvecs; i++) {
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if (sc->intvecs[i].irq == xirr)
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break;
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}
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KASSERT(i < sc->nintvecs, ("Unmapped XIRR"));
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powerpc_dispatch_intr(sc->intvecs[i].vector, tf);
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}
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}
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static void
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xicp_enable(device_t dev, u_int irq, u_int vector)
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{
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struct xicp_softc *sc;
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cell_t status, cpu;
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sc = device_get_softc(dev);
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KASSERT(sc->nintvecs + 1 < nitems(sc->intvecs),
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("Too many XICP interrupts"));
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/* Bind to this CPU to start: distrib. ID is last entry in gserver# */
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cpu = PCPU_GET(hwref);
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mtx_lock(&sc->sc_mtx);
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sc->intvecs[sc->nintvecs].irq = irq;
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sc->intvecs[sc->nintvecs].vector = vector;
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sc->intvecs[sc->nintvecs].cpu = cpu;
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mb();
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sc->nintvecs++;
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mtx_unlock(&sc->sc_mtx);
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/* IPIs are also enabled */
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if (irq == MAX_XICP_IRQS)
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return;
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if (rtas_exists()) {
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rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
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XICP_PRIORITY, &status);
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xicp_unmask(dev, irq);
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#ifdef POWERNV
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} else {
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status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
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/* Unmask implicit for OPAL */
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if (status != 0)
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panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq,
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cpu, status);
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#endif
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}
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}
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static void
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xicp_eoi(device_t dev, u_int irq)
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{
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#ifdef POWERNV
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struct xicp_softc *sc;
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#endif
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uint64_t xirr;
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if (irq == MAX_XICP_IRQS) /* Remap IPI interrupt to internal value */
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irq = XICP_IPI;
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xirr = irq | (0xff << 24);
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#ifdef POWERNV
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if (mfmsr() & PSL_HV) {
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sc = device_get_softc(dev);
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if (sc->xics_emu)
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opal_call(OPAL_INT_EOI, xirr);
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else
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bus_write_4(xicp_mem_for_cpu(PCPU_GET(hwref)), 4, xirr);
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} else
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#endif
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phyp_hcall(H_EOI, xirr);
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}
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static void
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xicp_ipi(device_t dev, u_int cpu)
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{
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#ifdef POWERNV
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struct xicp_softc *sc;
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cpu = pcpu_find(cpu)->pc_hwref;
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if (mfmsr() & PSL_HV) {
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sc = device_get_softc(dev);
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if (sc->xics_emu) {
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int64_t rv;
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rv = opal_call(OPAL_INT_SET_MFRR, cpu, XICP_PRIORITY);
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if (rv != 0)
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device_printf(dev, "IPI SET_MFRR result: %ld\n", rv);
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} else
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bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY);
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} else
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#endif
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phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
|
|
}
|
|
|
|
static void
|
|
xicp_mask(device_t dev, u_int irq)
|
|
{
|
|
struct xicp_softc *sc = device_get_softc(dev);
|
|
cell_t status;
|
|
|
|
if (irq == MAX_XICP_IRQS)
|
|
return;
|
|
|
|
if (rtas_exists()) {
|
|
rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
|
|
#ifdef POWERNV
|
|
} else {
|
|
int i;
|
|
|
|
for (i = 0; i < sc->nintvecs; i++) {
|
|
if (sc->intvecs[i].irq == irq) {
|
|
break;
|
|
}
|
|
}
|
|
KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt"));
|
|
opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static void
|
|
xicp_unmask(device_t dev, u_int irq)
|
|
{
|
|
struct xicp_softc *sc = device_get_softc(dev);
|
|
cell_t status;
|
|
|
|
if (irq == MAX_XICP_IRQS)
|
|
return;
|
|
|
|
if (rtas_exists()) {
|
|
rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
|
|
#ifdef POWERNV
|
|
} else {
|
|
int i;
|
|
|
|
for (i = 0; i < sc->nintvecs; i++) {
|
|
if (sc->intvecs[i].irq == irq) {
|
|
break;
|
|
}
|
|
}
|
|
KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt"));
|
|
opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2,
|
|
XICP_PRIORITY);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#ifdef POWERNV
|
|
/* This is only used on POWER9 systems with the XIVE's XICS emulation. */
|
|
void
|
|
xicp_smp_cpu_startup(void)
|
|
{
|
|
struct xicp_softc *sc;
|
|
|
|
if (mfmsr() & PSL_HV) {
|
|
sc = device_get_softc(root_pic);
|
|
|
|
if (sc->xics_emu)
|
|
opal_call(OPAL_INT_SET_CPPR, 0xff);
|
|
}
|
|
}
|
|
#endif
|