33a793a3e6
of the thread in cpu_switch(). It's otherwise possible that on another CPU the thread continues from stale context data. Note that this is prominent on newer CPUs, like the Montecito, that really take advantage of the weak memory ordering. First generation Itanium 2 is not that aggressive and does not need this. This is a direct commit to stable/10. Approved by: re@ (gjb) |
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acpica | ||
conf | ||
disasm | ||
ia32 | ||
ia64 | ||
include | ||
isa | ||
pci |