d754734f5c
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
502 lines
12 KiB
C
502 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/queue.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <x86/apicreg.h>
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#include <machine/vmm.h>
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#include "vmm_ktr.h"
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#include "vmm_lapic.h"
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#include "vlapic.h"
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#include "vioapic.h"
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#define IOREGSEL 0x00
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#define IOWIN 0x10
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#define REDIR_ENTRIES 32
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#define RTBL_RO_BITS ((uint64_t)(IOART_REM_IRR | IOART_DELIVS))
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struct vioapic {
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struct vm *vm;
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struct mtx mtx;
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uint32_t id;
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uint32_t ioregsel;
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struct {
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uint64_t reg;
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int acnt; /* sum of pin asserts (+1) and deasserts (-1) */
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} rtbl[REDIR_ENTRIES];
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};
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#define VIOAPIC_LOCK(vioapic) mtx_lock_spin(&((vioapic)->mtx))
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#define VIOAPIC_UNLOCK(vioapic) mtx_unlock_spin(&((vioapic)->mtx))
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#define VIOAPIC_LOCKED(vioapic) mtx_owned(&((vioapic)->mtx))
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static MALLOC_DEFINE(M_VIOAPIC, "vioapic", "bhyve virtual ioapic");
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#define VIOAPIC_CTR1(vioapic, fmt, a1) \
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VM_CTR1((vioapic)->vm, fmt, a1)
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#define VIOAPIC_CTR2(vioapic, fmt, a1, a2) \
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VM_CTR2((vioapic)->vm, fmt, a1, a2)
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#define VIOAPIC_CTR3(vioapic, fmt, a1, a2, a3) \
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VM_CTR3((vioapic)->vm, fmt, a1, a2, a3)
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#define VIOAPIC_CTR4(vioapic, fmt, a1, a2, a3, a4) \
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VM_CTR4((vioapic)->vm, fmt, a1, a2, a3, a4)
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#ifdef KTR
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static const char *
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pinstate_str(bool asserted)
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{
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if (asserted)
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return ("asserted");
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else
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return ("deasserted");
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}
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#endif
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static void
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vioapic_send_intr(struct vioapic *vioapic, int pin)
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{
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int vector, delmode;
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uint32_t low, high, dest;
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bool level, phys;
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KASSERT(pin >= 0 && pin < REDIR_ENTRIES,
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("vioapic_set_pinstate: invalid pin number %d", pin));
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KASSERT(VIOAPIC_LOCKED(vioapic),
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("vioapic_set_pinstate: vioapic is not locked"));
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low = vioapic->rtbl[pin].reg;
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high = vioapic->rtbl[pin].reg >> 32;
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if ((low & IOART_INTMASK) == IOART_INTMSET) {
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VIOAPIC_CTR1(vioapic, "ioapic pin%d: masked", pin);
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return;
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}
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phys = ((low & IOART_DESTMOD) == IOART_DESTPHY);
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delmode = low & IOART_DELMOD;
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level = low & IOART_TRGRLVL ? true : false;
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if (level)
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vioapic->rtbl[pin].reg |= IOART_REM_IRR;
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vector = low & IOART_INTVEC;
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dest = high >> APIC_ID_SHIFT;
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vlapic_deliver_intr(vioapic->vm, level, dest, phys, delmode, vector);
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}
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static void
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vioapic_set_pinstate(struct vioapic *vioapic, int pin, bool newstate)
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{
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int oldcnt, newcnt;
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bool needintr;
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KASSERT(pin >= 0 && pin < REDIR_ENTRIES,
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("vioapic_set_pinstate: invalid pin number %d", pin));
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KASSERT(VIOAPIC_LOCKED(vioapic),
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("vioapic_set_pinstate: vioapic is not locked"));
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oldcnt = vioapic->rtbl[pin].acnt;
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if (newstate)
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vioapic->rtbl[pin].acnt++;
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else
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vioapic->rtbl[pin].acnt--;
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newcnt = vioapic->rtbl[pin].acnt;
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if (newcnt < 0) {
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VIOAPIC_CTR2(vioapic, "ioapic pin%d: bad acnt %d",
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pin, newcnt);
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}
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needintr = false;
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if (oldcnt == 0 && newcnt == 1) {
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needintr = true;
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VIOAPIC_CTR1(vioapic, "ioapic pin%d: asserted", pin);
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} else if (oldcnt == 1 && newcnt == 0) {
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VIOAPIC_CTR1(vioapic, "ioapic pin%d: deasserted", pin);
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} else {
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VIOAPIC_CTR3(vioapic, "ioapic pin%d: %s, ignored, acnt %d",
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pin, pinstate_str(newstate), newcnt);
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}
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if (needintr)
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vioapic_send_intr(vioapic, pin);
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}
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enum irqstate {
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IRQSTATE_ASSERT,
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IRQSTATE_DEASSERT,
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IRQSTATE_PULSE
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};
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static int
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vioapic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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{
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struct vioapic *vioapic;
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if (irq < 0 || irq >= REDIR_ENTRIES)
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return (EINVAL);
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vioapic = vm_ioapic(vm);
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VIOAPIC_LOCK(vioapic);
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switch (irqstate) {
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case IRQSTATE_ASSERT:
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vioapic_set_pinstate(vioapic, irq, true);
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break;
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case IRQSTATE_DEASSERT:
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vioapic_set_pinstate(vioapic, irq, false);
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break;
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case IRQSTATE_PULSE:
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vioapic_set_pinstate(vioapic, irq, true);
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vioapic_set_pinstate(vioapic, irq, false);
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break;
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default:
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panic("vioapic_set_irqstate: invalid irqstate %d", irqstate);
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}
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VIOAPIC_UNLOCK(vioapic);
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return (0);
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}
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int
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vioapic_assert_irq(struct vm *vm, int irq)
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{
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return (vioapic_set_irqstate(vm, irq, IRQSTATE_ASSERT));
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}
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int
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vioapic_deassert_irq(struct vm *vm, int irq)
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{
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return (vioapic_set_irqstate(vm, irq, IRQSTATE_DEASSERT));
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}
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int
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vioapic_pulse_irq(struct vm *vm, int irq)
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{
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return (vioapic_set_irqstate(vm, irq, IRQSTATE_PULSE));
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}
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/*
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* Reset the vlapic's trigger-mode register to reflect the ioapic pin
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* configuration.
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*/
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static void
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vioapic_update_tmr(struct vm *vm, int vcpuid, void *arg)
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{
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struct vioapic *vioapic;
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struct vlapic *vlapic;
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uint32_t low, high, dest;
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int delmode, pin, vector;
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bool level, phys;
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vlapic = vm_lapic(vm, vcpuid);
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vioapic = vm_ioapic(vm);
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VIOAPIC_LOCK(vioapic);
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/*
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* Reset all vectors to be edge-triggered.
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*/
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vlapic_reset_tmr(vlapic);
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for (pin = 0; pin < REDIR_ENTRIES; pin++) {
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low = vioapic->rtbl[pin].reg;
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high = vioapic->rtbl[pin].reg >> 32;
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level = low & IOART_TRGRLVL ? true : false;
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if (!level)
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continue;
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/*
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* For a level-triggered 'pin' let the vlapic figure out if
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* an assertion on this 'pin' would result in an interrupt
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* being delivered to it. If yes, then it will modify the
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* TMR bit associated with this vector to level-triggered.
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*/
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phys = ((low & IOART_DESTMOD) == IOART_DESTPHY);
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delmode = low & IOART_DELMOD;
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vector = low & IOART_INTVEC;
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dest = high >> APIC_ID_SHIFT;
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vlapic_set_tmr_level(vlapic, dest, phys, delmode, vector);
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}
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VIOAPIC_UNLOCK(vioapic);
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}
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static uint32_t
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vioapic_read(struct vioapic *vioapic, int vcpuid, uint32_t addr)
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{
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int regnum, pin, rshift;
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regnum = addr & 0xff;
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switch (regnum) {
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case IOAPIC_ID:
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return (vioapic->id);
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break;
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case IOAPIC_VER:
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return (((REDIR_ENTRIES - 1) << MAXREDIRSHIFT) | 0x11);
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break;
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case IOAPIC_ARB:
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return (vioapic->id);
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break;
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default:
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break;
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}
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/* redirection table entries */
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if (regnum >= IOAPIC_REDTBL &&
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regnum < IOAPIC_REDTBL + REDIR_ENTRIES * 2) {
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pin = (regnum - IOAPIC_REDTBL) / 2;
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if ((regnum - IOAPIC_REDTBL) % 2)
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rshift = 32;
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else
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rshift = 0;
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return (vioapic->rtbl[pin].reg >> rshift);
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}
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return (0);
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}
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static void
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vioapic_write(struct vioapic *vioapic, int vcpuid, uint32_t addr, uint32_t data)
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{
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uint64_t data64, mask64;
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uint64_t last, changed;
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int regnum, pin, lshift;
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cpuset_t allvcpus;
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regnum = addr & 0xff;
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switch (regnum) {
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case IOAPIC_ID:
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vioapic->id = data & APIC_ID_MASK;
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break;
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case IOAPIC_VER:
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case IOAPIC_ARB:
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/* readonly */
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break;
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default:
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break;
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}
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/* redirection table entries */
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if (regnum >= IOAPIC_REDTBL &&
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regnum < IOAPIC_REDTBL + REDIR_ENTRIES * 2) {
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pin = (regnum - IOAPIC_REDTBL) / 2;
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if ((regnum - IOAPIC_REDTBL) % 2)
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lshift = 32;
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else
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lshift = 0;
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last = vioapic->rtbl[pin].reg;
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data64 = (uint64_t)data << lshift;
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mask64 = (uint64_t)0xffffffff << lshift;
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vioapic->rtbl[pin].reg &= ~mask64 | RTBL_RO_BITS;
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vioapic->rtbl[pin].reg |= data64 & ~RTBL_RO_BITS;
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VIOAPIC_CTR2(vioapic, "ioapic pin%d: redir table entry %#lx",
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pin, vioapic->rtbl[pin].reg);
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/*
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* If any fields in the redirection table entry (except mask
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* or polarity) have changed then rendezvous all the vcpus
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* to update their vlapic trigger-mode registers.
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*/
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changed = last ^ vioapic->rtbl[pin].reg;
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if (changed & ~(IOART_INTMASK | IOART_INTPOL)) {
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VIOAPIC_CTR1(vioapic, "ioapic pin%d: recalculate "
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"vlapic trigger-mode register", pin);
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VIOAPIC_UNLOCK(vioapic);
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allvcpus = vm_active_cpus(vioapic->vm);
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vm_smp_rendezvous(vioapic->vm, vcpuid, allvcpus,
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vioapic_update_tmr, NULL);
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VIOAPIC_LOCK(vioapic);
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}
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/*
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* Generate an interrupt if the following conditions are met:
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* - pin is not masked
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* - previous interrupt has been EOIed
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* - pin level is asserted
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*/
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if ((vioapic->rtbl[pin].reg & IOART_INTMASK) == IOART_INTMCLR &&
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(vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0 &&
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(vioapic->rtbl[pin].acnt > 0)) {
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VIOAPIC_CTR2(vioapic, "ioapic pin%d: asserted at rtbl "
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"write, acnt %d", pin, vioapic->rtbl[pin].acnt);
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vioapic_send_intr(vioapic, pin);
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}
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}
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}
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static int
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vioapic_mmio_rw(struct vioapic *vioapic, int vcpuid, uint64_t gpa,
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uint64_t *data, int size, bool doread)
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{
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uint64_t offset;
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offset = gpa - VIOAPIC_BASE;
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/*
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* The IOAPIC specification allows 32-bit wide accesses to the
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* IOREGSEL (offset 0) and IOWIN (offset 16) registers.
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*/
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if (size != 4 || (offset != IOREGSEL && offset != IOWIN)) {
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if (doread)
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*data = 0;
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return (0);
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}
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VIOAPIC_LOCK(vioapic);
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if (offset == IOREGSEL) {
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if (doread)
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*data = vioapic->ioregsel;
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else
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vioapic->ioregsel = *data;
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} else {
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if (doread) {
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*data = vioapic_read(vioapic, vcpuid,
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vioapic->ioregsel);
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} else {
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vioapic_write(vioapic, vcpuid, vioapic->ioregsel,
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*data);
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}
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}
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VIOAPIC_UNLOCK(vioapic);
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return (0);
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}
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int
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vioapic_mmio_read(void *vm, int vcpuid, uint64_t gpa, uint64_t *rval,
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int size, void *arg)
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{
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int error;
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struct vioapic *vioapic;
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vioapic = vm_ioapic(vm);
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error = vioapic_mmio_rw(vioapic, vcpuid, gpa, rval, size, true);
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return (error);
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}
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int
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vioapic_mmio_write(void *vm, int vcpuid, uint64_t gpa, uint64_t wval,
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int size, void *arg)
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{
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int error;
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struct vioapic *vioapic;
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vioapic = vm_ioapic(vm);
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error = vioapic_mmio_rw(vioapic, vcpuid, gpa, &wval, size, false);
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return (error);
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}
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void
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vioapic_process_eoi(struct vm *vm, int vcpuid, int vector)
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{
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struct vioapic *vioapic;
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int pin;
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KASSERT(vector >= 0 && vector < 256,
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("vioapic_process_eoi: invalid vector %d", vector));
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vioapic = vm_ioapic(vm);
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VIOAPIC_CTR1(vioapic, "ioapic processing eoi for vector %d", vector);
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/*
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* XXX keep track of the pins associated with this vector instead
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* of iterating on every single pin each time.
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*/
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VIOAPIC_LOCK(vioapic);
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for (pin = 0; pin < REDIR_ENTRIES; pin++) {
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if ((vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0)
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continue;
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if ((vioapic->rtbl[pin].reg & IOART_INTVEC) != vector)
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continue;
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vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;
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if (vioapic->rtbl[pin].acnt > 0) {
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VIOAPIC_CTR2(vioapic, "ioapic pin%d: asserted at eoi, "
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"acnt %d", pin, vioapic->rtbl[pin].acnt);
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vioapic_send_intr(vioapic, pin);
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}
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}
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VIOAPIC_UNLOCK(vioapic);
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}
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struct vioapic *
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vioapic_init(struct vm *vm)
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{
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int i;
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struct vioapic *vioapic;
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vioapic = malloc(sizeof(struct vioapic), M_VIOAPIC, M_WAITOK | M_ZERO);
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vioapic->vm = vm;
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mtx_init(&vioapic->mtx, "vioapic lock", NULL, MTX_SPIN);
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/* Initialize all redirection entries to mask all interrupts */
|
|
for (i = 0; i < REDIR_ENTRIES; i++)
|
|
vioapic->rtbl[i].reg = 0x0001000000010000UL;
|
|
|
|
return (vioapic);
|
|
}
|
|
|
|
void
|
|
vioapic_cleanup(struct vioapic *vioapic)
|
|
{
|
|
|
|
free(vioapic, M_VIOAPIC);
|
|
}
|
|
|
|
int
|
|
vioapic_pincount(struct vm *vm)
|
|
{
|
|
|
|
return (REDIR_ENTRIES);
|
|
}
|