87 lines
3.0 KiB
C
87 lines
3.0 KiB
C
/*-
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* Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_LSU_H_
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#define _MACHINE_LSU_H_
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/*
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* Definitions for the Load-Store-Unit Control Register. This is called
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* Data Cache Unit Control Register (DCUCR) for UltraSPARC-III and greater.
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*/
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#define LSU_IC (1UL << 0)
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#define LSU_DC (1UL << 1)
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#define LSU_IM (1UL << 2)
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#define LSU_DM (1UL << 3)
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/* Parity control mask, UltraSPARC-I and II series only. */
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#define LSU_FM_SHIFT 4
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#define LSU_FM_BITS 16
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#define LSU_FM_MASK (((1UL << LSU_FM_BITS) - 1) << LSU_FM_SHIFT)
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#define LSU_VM_SHIFT 25
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#define LSU_VM_BITS 8
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#define LSU_VM_MASK (((1UL << LSU_VM_BITS) - 1) << LSU_VM_SHIFT)
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#define LSU_PM_SHIFT 33
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#define LSU_PM_BITS 8
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#define LSU_PM_MASK (((1UL << LSU_PM_BITS) - 1) << LSU_PM_SHIFT)
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#define LSU_VW (1UL << 21)
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#define LSU_VR (1UL << 22)
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#define LSU_PW (1UL << 23)
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#define LSU_PR (1UL << 24)
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/* The following bits are valid for the UltraSPARC-III series only. */
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#define LSU_WE (1UL << 41)
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#define LSU_SL (1UL << 42)
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#define LSU_SPE (1UL << 43)
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#define LSU_HPE (1UL << 44)
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#define LSU_PE (1UL << 45)
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#define LSU_RE (1UL << 46)
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#define LSU_ME (1UL << 47)
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#define LSU_CV (1UL << 48)
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#define LSU_CP (1UL << 49)
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/* The following bit is valid for the UltraSPARC-IV only. */
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#define LSU_WIH (1UL << 4)
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/* The following bits are valid for the UltraSPARC-IV+ only. */
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#define LSU_PPS_SHIFT 50
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#define LSU_PPS_BITS 2
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#define LSU_PPS_MASK (((1UL << LSU_PPS_BITS) - 1) << LSU_PPS_SHIFT)
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#define LSU_IPS_SHIFT 52
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#define LSU_IPS_BITS 2
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#define LSU_IPS_MASK (((1UL << LSU_IPS_BITS) - 1) << LSU_IPS_SHIFT)
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#define LSU_PCM (1UL << 54)
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#define LSU_WCE (1UL << 55)
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/* The following bit is valid for the SPARC64 V, VI, VII and VIIIfx only. */
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#define LSU_WEAK_SPCA (1UL << 41)
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#endif /* _MACHINE_LSU_H_ */
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