sbruno 8d4db71d65 Update Features2 to display SDBG capability of processor. This is ...

showing up on Haswell-class CPUs

From the Intel SDM, "Table 3-20. Feature Information Returned in the
ECX Register"

11 | SDBG | A value of 1 indicates the processor supports
IA32_DEBUG_INTERFACE MSR for silicon debug.

Submitted by:	jiashiun@gmail.com
Reviewed by:	jhb neel
MFC after:	2 weeks

2015-01-08 16:50:35 +00:00

..

acpica

Create a cpuset mask for each NUMA domain that is available in the

2015-01-08 15:53:13 +00:00

bios

Add missing header needed by free(9).

2012-09-30 15:42:20 +00:00

cpufreq

Pull in r267961 and r267973 again. Fix for issues reported will follow.

2014-06-28 03:56:17 +00:00

include

Update Features2 to display SDBG capability of processor. This is

2015-01-08 16:50:35 +00:00

iommu

Follow up to r225617. In order to maximize the re-usability of kernel code

2014-10-16 18:04:43 +00:00

isa

Virtual machines can easily have more than 16 option ROMs and

2014-10-22 01:37:32 +00:00

pci

Pull in r267961 and r267973 again. Fix for issues reported will follow.

2014-06-28 03:56:17 +00:00

x86

Update Features2 to display SDBG capability of processor. This is

2015-01-08 16:50:35 +00:00

xen

Fix warning about possible use of uninitialized variable.

2015-01-02 08:42:44 +00:00