gibbs a16faf06d2 Change the way DMA is handled during the command phase. Only test on ... SDONE, not HDONE. In the data phase dma handler, mask off just the enable bits instead of clearing the whole register. Clearing the direction bit could be bad. Also don't stop a DMA until MREQPEND goes false. Doing this may cause an ABORT on the PCI bus although I have yet to see this happen. Add definitions for MREQPEND and the BRDCTL register. The BRDCTL register is used to handle high byte termination and automatic termination testing.		1997-01-24 21:57:47 +00:00
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aicasm	Make the long-awaited change from $Id$ to $FreeBSD$	1997-01-14 07:20:47 +00:00
aic7xxx_asm.1	John Aycock's BSD copyrighted sequencer assembler and sequencer code. This	1995-04-15 21:45:56 +00:00
aic7xxx_asm.c	Make the long-awaited change from $Id$ to $FreeBSD$	1997-01-14 07:20:47 +00:00
aic7xxx_reg.h	Change the way DMA is handled during the command phase. Only test on	1997-01-24 21:57:47 +00:00
aic7xxx.seq	Change the way DMA is handled during the command phase. Only test on	1997-01-24 21:57:47 +00:00
aicasm.c	Make the long-awaited change from $Id$ to $FreeBSD$	1997-01-14 07:20:47 +00:00