db7f0b974f
and ifnet functions - add memory barriers to <machine/atomic.h> - update drivers to only conditionally define their own - add lockless producer / consumer ring buffer - remove ring buffer implementation from cxgb and update its callers - add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to allow drivers to efficiently manage multiple hardware queues (i.e. not serialize all packets through one ifq) - expose if_qflush to allow drivers to flush any driver managed queues This work was supported by Bitgravity Inc. and Chelsio Inc.
300 lines
8.7 KiB
C
300 lines
8.7 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson.
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: FreeBSD: src/sys/i386/include/atomic.h,v 1.20 2001/02/11
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#include <machine/cpufunc.h>
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#define mb() __asm__ __volatile__ ("membar #MemIssue": : :"memory")
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#define wmb() mb()
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#define rmb() mb()
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/* Userland needs different ASI's. */
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#ifdef _KERNEL
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#define __ASI_ATOMIC ASI_N
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#else
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#define __ASI_ATOMIC ASI_P
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#endif
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/*
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* Various simple arithmetic on memory which is atomic in the presence
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* of interrupts and multiple processors. See atomic(9) for details.
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* Note that efficient hardware support exists only for the 32 and 64
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* bit variants; the 8 and 16 bit versions are not provided and should
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* not be used in MI code.
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*
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* This implementation takes advantage of the fact that the sparc64
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* cas instruction is both a load and a store. The loop is often coded
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* as follows:
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*
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* do {
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* expect = *p;
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* new = expect + 1;
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* } while (cas(p, expect, new) != expect);
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*
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* which performs an unnnecessary load on each iteration that the cas
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* operation fails. Modified as follows:
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*
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* expect = *p;
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* for (;;) {
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* new = expect + 1;
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* result = cas(p, expect, new);
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* if (result == expect)
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* break;
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* expect = result;
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* }
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*
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* the return value of cas is used to avoid the extra reload.
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*
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* The memory barriers provided by the acq and rel variants are intended
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* to be sufficient for use of relaxed memory ordering. Due to the
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* suggested assembly syntax of the membar operands containing a #
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* character, they cannot be used in macros. The cmask and mmask bits
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* are hard coded in machine/cpufunc.h and used here through macros.
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* Hopefully sun will choose not to change the bit numbers.
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*/
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#define itype(sz) uint ## sz ## _t
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#define atomic_cas_32(p, e, s) casa(p, e, s, __ASI_ATOMIC)
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#define atomic_cas_64(p, e, s) casxa(p, e, s, __ASI_ATOMIC)
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#define atomic_cas(p, e, s, sz) \
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atomic_cas_ ## sz(p, e, s)
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#define atomic_cas_acq(p, e, s, sz) ({ \
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itype(sz) v; \
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v = atomic_cas(p, e, s, sz); \
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membar(LoadLoad | LoadStore); \
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v; \
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})
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#define atomic_cas_rel(p, e, s, sz) ({ \
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itype(sz) v; \
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membar(LoadStore | StoreStore); \
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v = atomic_cas(p, e, s, sz); \
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v; \
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})
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#define atomic_op(p, op, v, sz) ({ \
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itype(sz) e, r, s; \
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for (e = *(volatile itype(sz) *)p;; e = r) { \
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s = e op v; \
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r = atomic_cas_ ## sz(p, e, s); \
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if (r == e) \
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break; \
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} \
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e; \
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})
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#define atomic_op_acq(p, op, v, sz) ({ \
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itype(sz) t; \
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t = atomic_op(p, op, v, sz); \
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membar(LoadLoad | LoadStore); \
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t; \
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})
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#define atomic_op_rel(p, op, v, sz) ({ \
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itype(sz) t; \
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membar(LoadStore | StoreStore); \
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t = atomic_op(p, op, v, sz); \
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t; \
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})
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#define atomic_load(p, sz) \
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atomic_cas(p, 0, 0, sz)
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#define atomic_load_acq(p, sz) ({ \
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itype(sz) v; \
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v = atomic_load(p, sz); \
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membar(LoadLoad | LoadStore); \
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v; \
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})
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#define atomic_load_clear(p, sz) ({ \
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itype(sz) e, r; \
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for (e = *(volatile itype(sz) *)p;; e = r) { \
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r = atomic_cas(p, e, 0, sz); \
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if (r == e) \
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break; \
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} \
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e; \
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})
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#define atomic_store(p, v, sz) do { \
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itype(sz) e, r; \
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for (e = *(volatile itype(sz) *)p;; e = r) { \
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r = atomic_cas(p, e, v, sz); \
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if (r == e) \
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break; \
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} \
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} while (0)
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#define atomic_store_rel(p, v, sz) do { \
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membar(LoadStore | StoreStore); \
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atomic_store(p, v, sz); \
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} while (0)
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#define ATOMIC_GEN(name, ptype, vtype, atype, sz) \
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\
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static __inline vtype \
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atomic_add_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op(p, +, v, sz)); \
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} \
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static __inline vtype \
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atomic_add_acq_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_acq(p, +, v, sz)); \
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} \
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static __inline vtype \
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atomic_add_rel_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_rel(p, +, v, sz)); \
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} \
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\
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static __inline vtype \
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atomic_clear_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op(p, &, ~v, sz)); \
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} \
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static __inline vtype \
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atomic_clear_acq_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_acq(p, &, ~v, sz)); \
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} \
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static __inline vtype \
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atomic_clear_rel_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_rel(p, &, ~v, sz)); \
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} \
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\
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static __inline int \
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atomic_cmpset_ ## name(volatile ptype p, vtype e, vtype s) \
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{ \
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return (((vtype)atomic_cas(p, e, s, sz)) == e); \
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} \
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static __inline int \
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atomic_cmpset_acq_ ## name(volatile ptype p, vtype e, vtype s) \
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{ \
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return (((vtype)atomic_cas_acq(p, e, s, sz)) == e); \
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} \
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static __inline int \
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atomic_cmpset_rel_ ## name(volatile ptype p, vtype e, vtype s) \
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{ \
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return (((vtype)atomic_cas_rel(p, e, s, sz)) == e); \
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} \
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\
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static __inline vtype \
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atomic_load_ ## name(volatile ptype p) \
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{ \
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return ((vtype)atomic_cas(p, 0, 0, sz)); \
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} \
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static __inline vtype \
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atomic_load_acq_ ## name(volatile ptype p) \
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{ \
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return ((vtype)atomic_cas_acq(p, 0, 0, sz)); \
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} \
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\
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static __inline vtype \
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atomic_readandclear_ ## name(volatile ptype p) \
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{ \
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return ((vtype)atomic_load_clear(p, sz)); \
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} \
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\
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static __inline vtype \
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atomic_set_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op(p, |, v, sz)); \
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} \
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static __inline vtype \
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atomic_set_acq_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_acq(p, |, v, sz)); \
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} \
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static __inline vtype \
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atomic_set_rel_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_rel(p, |, v, sz)); \
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} \
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\
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static __inline vtype \
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atomic_subtract_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op(p, -, v, sz)); \
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} \
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static __inline vtype \
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atomic_subtract_acq_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_acq(p, -, v, sz)); \
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} \
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static __inline vtype \
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atomic_subtract_rel_ ## name(volatile ptype p, atype v) \
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{ \
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return ((vtype)atomic_op_rel(p, -, v, sz)); \
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} \
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\
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static __inline void \
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atomic_store_ ## name(volatile ptype p, vtype v) \
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{ \
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atomic_store(p, v, sz); \
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} \
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static __inline void \
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atomic_store_rel_ ## name(volatile ptype p, vtype v) \
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{ \
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atomic_store_rel(p, v, sz); \
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}
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ATOMIC_GEN(int, u_int *, u_int, u_int, 32);
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ATOMIC_GEN(32, uint32_t *, uint32_t, uint32_t, 32);
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ATOMIC_GEN(long, u_long *, u_long, u_long, 64);
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ATOMIC_GEN(64, uint64_t *, uint64_t, uint64_t, 64);
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ATOMIC_GEN(ptr, uintptr_t *, uintptr_t, uintptr_t, 64);
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#define atomic_fetchadd_int atomic_add_int
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#define atomic_fetchadd_32 atomic_add_32
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#define atomic_fetchadd_long atomic_add_long
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#undef ATOMIC_GEN
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#undef atomic_cas
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#undef atomic_cas_acq
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#undef atomic_cas_rel
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#undef atomic_op
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#undef atomic_op_acq
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#undef atomic_op_rel
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#undef atomic_load_acq
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#undef atomic_store_rel
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#undef atomic_load_clear
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#endif /* !_MACHINE_ATOMIC_H_ */
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