405ada37fb
This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week
219 lines
5.7 KiB
C
219 lines
5.7 KiB
C
/*-
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_UART_BUS_H_
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#define _DEV_UART_BUS_H_
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#ifndef KLD_MODULE
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#include "opt_uart.h"
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#endif
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#include <sys/serial.h>
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#include <sys/timepps.h>
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/* Drain and flush targets. */
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#define UART_DRAIN_RECEIVER 0x0001
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#define UART_DRAIN_TRANSMITTER 0x0002
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#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
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#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
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/* Received character status bits. */
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#define UART_STAT_BREAK 0x0100
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#define UART_STAT_FRAMERR 0x0200
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#define UART_STAT_OVERRUN 0x0400
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#define UART_STAT_PARERR 0x0800
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#ifdef UART_PPS_ON_CTS
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#define UART_SIG_DPPS SER_DCTS
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#define UART_SIG_PPS SER_CTS
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#else
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#define UART_SIG_DPPS SER_DDCD
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#define UART_SIG_PPS SER_DCD
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#endif
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/* UART_IOCTL() requests */
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#define UART_IOCTL_BREAK 1
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#define UART_IOCTL_IFLOW 2
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#define UART_IOCTL_OFLOW 3
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#define UART_IOCTL_BAUD 4
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/*
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* UART class & instance (=softc)
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*/
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struct uart_class {
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KOBJ_CLASS_FIELDS;
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struct uart_ops *uc_ops; /* Low-level console operations. */
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u_int uc_range; /* Bus space address range. */
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u_int uc_rclk; /* Default rclk for this device. */
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u_int uc_rshift; /* Default regshift for this device. */
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};
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struct uart_softc {
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KOBJ_FIELDS;
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struct uart_class *sc_class;
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struct uart_bas sc_bas;
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device_t sc_dev;
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struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */
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struct mtx *sc_hwmtx;
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struct resource *sc_rres; /* Register resource. */
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int sc_rrid;
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int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
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struct resource *sc_ires; /* Interrupt resource. */
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void *sc_icookie;
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int sc_irid;
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struct callout sc_timer;
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int sc_callout:1; /* This UART is opened for callout. */
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int sc_fastintr:1; /* This UART uses fast interrupts. */
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int sc_hwiflow:1; /* This UART has HW input flow ctl. */
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int sc_hwoflow:1; /* This UART has HW output flow ctl. */
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int sc_leaving:1; /* This UART is going away. */
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int sc_opened:1; /* This UART is open for business. */
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int sc_polled:1; /* This UART has no interrupts. */
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int sc_txbusy:1; /* This UART is transmitting. */
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int sc_isquelch:1; /* This UART has input squelched. */
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struct uart_devinfo *sc_sysdev; /* System device (or NULL). */
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int sc_altbrk; /* State for alt break sequence. */
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uint32_t sc_hwsig; /* Signal state. Used by HW driver. */
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/* Receiver data. */
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uint16_t *sc_rxbuf;
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int sc_rxbufsz;
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int sc_rxput;
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int sc_rxget;
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int sc_rxfifosz; /* Size of RX FIFO. */
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/* Transmitter data. */
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uint8_t *sc_txbuf;
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int sc_txdatasz;
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int sc_txfifosz; /* Size of TX FIFO and buffer. */
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/* Pulse capturing support (PPS). */
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struct pps_state sc_pps;
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/* Upper layer data. */
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void *sc_softih;
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uint32_t sc_ttypend;
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union {
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/* TTY specific data. */
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struct {
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struct tty *tp;
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} u_tty;
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/* Keyboard specific data. */
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struct {
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} u_kbd;
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} sc_u;
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};
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extern devclass_t uart_devclass;
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extern char uart_driver_name[];
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int uart_bus_attach(device_t dev);
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int uart_bus_detach(device_t dev);
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int uart_bus_resume(device_t dev);
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serdev_intr_t *uart_bus_ihand(device_t dev, int ipend);
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int uart_bus_ipend(device_t dev);
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int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan);
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int uart_bus_sysdev(device_t dev);
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void uart_sched_softih(struct uart_softc *, uint32_t);
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int uart_tty_attach(struct uart_softc *);
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int uart_tty_detach(struct uart_softc *);
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void uart_tty_intr(void *arg);
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/*
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* Receive buffer operations.
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*/
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static __inline int
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uart_rx_empty(struct uart_softc *sc)
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{
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return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0);
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}
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static __inline int
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uart_rx_full(struct uart_softc *sc)
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{
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return ((sc->sc_rxput + 1 < sc->sc_rxbufsz)
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? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0));
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}
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static __inline int
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uart_rx_get(struct uart_softc *sc)
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{
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int ptr, xc;
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ptr = sc->sc_rxget;
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if (ptr == sc->sc_rxput)
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return (-1);
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xc = sc->sc_rxbuf[ptr++];
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sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
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return (xc);
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}
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static __inline int
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uart_rx_next(struct uart_softc *sc)
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{
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int ptr;
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ptr = sc->sc_rxget;
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if (ptr == sc->sc_rxput)
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return (-1);
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ptr += 1;
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sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
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return (0);
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}
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static __inline int
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uart_rx_peek(struct uart_softc *sc)
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{
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int ptr;
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ptr = sc->sc_rxget;
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return ((ptr == sc->sc_rxput) ? -1 : sc->sc_rxbuf[ptr]);
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}
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static __inline int
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uart_rx_put(struct uart_softc *sc, int xc)
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{
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int ptr;
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ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
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if (ptr == sc->sc_rxget)
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return (ENOSPC);
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sc->sc_rxbuf[sc->sc_rxput] = xc;
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sc->sc_rxput = ptr;
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return (0);
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}
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#endif /* _DEV_UART_BUS_H_ */
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