freebsd-skq/sys/dev/sdhci
marius 409a575ad0 o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
  - Switching the signal voltage (VCCQ) to 1.8 V or (if supported
    by the host controller) to 1.2 V,
  - setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
    register,
  - setting the power class in the eMMC device according to the
    core supply voltage (VCC),
  - using different bits for enabling a bus width of 4 and 8 bits
    in the the eMMC device at DDR or higher timings respectively,
  - arbitrating timings faster than high speed if there actually
    are additional devices on the same MMC bus.

  Given that support for DDR52 is not denoted by SDHCI capability
  registers, availability of that timing is indicated by a new
  quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
  controllers so far. Generally, what it takes for a sdhci(4)
  front-end to enable support for DDR52 is to hook up the bridge
  method mmcbr_switch_vccq (which especially for 1.2 V signaling
  support is chip/board specific) and the sdhci_set_uhs_timing
  sdhci(4) method.

  As a side-effect, this change also fixes communication with
  some eMMC devices at SDR high speed mode with 52 MHz due to
  the signaling voltage and UHS bits in the SDHCI controller no
  longer being left in an inappropriate state.

  Compared to 52 MHz at SDR high speed which typically yields
  ~45 MB/s with the eMMC chips tested, throughput goes up to
  ~80 MB/s at DDR52.

  Additionally, this change already adds infrastructure and quite
  some code for modes up to HS400ES and SDR104 respectively (I did
  not want to add to much stuff at a time, though). Essentially,
  what is still missing in order to be able to activate support
  for these latter is is support for and handling of (re-)tuning.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
  hw.sdhci.quirk_set, which (when hooked up in the front-end)
  allow to set/clear sdhci(4) quirks for debugging and testing
  purposes. However, especially for SDHCI controllers on the
  PCI bus which have no specific support code so far and, thus,
  are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
  allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
  function calls instead of assuming that everything went right.
  In case failures actually are not problematic, indicate that
  by casting the return value to void.

Reviewed by:	jmcneill
2017-03-19 23:27:17 +00:00
..
fsl_sdhci.c Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges 2017-03-07 22:42:44 +00:00
sdhci_acpi.c o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and 2017-03-19 23:27:17 +00:00
sdhci_fdt_gpio.c Release all previously allocated resources. 2017-03-08 14:52:03 +00:00
sdhci_fdt_gpio.h Add new helper routines for sdhci bridge drivers that use gpio pins for 2017-01-09 01:54:36 +00:00
sdhci_fdt.c Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges 2017-03-07 22:42:44 +00:00
sdhci_if.m o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and 2017-03-19 23:27:17 +00:00
sdhci_pci.c o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and 2017-03-19 23:27:17 +00:00
sdhci.c o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and 2017-03-19 23:27:17 +00:00
sdhci.h o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and 2017-03-19 23:27:17 +00:00