168 lines
5.1 KiB
C
168 lines
5.1 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SAF1761_OTG_H_
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#define _SAF1761_OTG_H_
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#define SOTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32)
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#define SOTG_FS_MAX_PACKET_SIZE 64
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#define SOTG_HS_MAX_PACKET_SIZE 512
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#define SOTG_NUM_PORTS 2 /* one Device and one Host port */
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#define SOTG_HOST_PORT_NUM 1
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#define SOTG_DEVICE_PORT_NUM 2
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#define SOTG_HOST_CHANNEL_MAX (3 * 32)
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/* Macros used for reading and writing little endian registers */
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#define SAF1761_READ_LE_4(sc, reg) ({ uint32_t _temp; \
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_temp = bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg)); \
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le32toh(_temp); })
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#define SAF1761_WRITE_LE_4(sc, reg, data) do { \
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uint32_t _temp = (data); \
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bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg), htole32(_temp)); \
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} while (0)
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/* 90ns delay macro */
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#define SAF1761_90NS_DELAY(sc) do { \
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(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
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(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
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(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
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(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
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} while (0)
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struct saf1761_otg_softc;
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struct saf1761_otg_td;
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typedef uint8_t (saf1761_otg_cmd_t)(struct saf1761_otg_softc *, struct saf1761_otg_td *td);
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struct saf1761_otg_td {
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struct saf1761_otg_td *obj_next;
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saf1761_otg_cmd_t *func;
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struct usb_page_cache *pc;
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uint32_t offset;
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uint32_t remainder;
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uint32_t dw1_value;
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uint16_t max_packet_size;
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uint8_t ep_index;
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uint8_t ep_type;
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uint8_t channel;
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uint8_t uframe;
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uint8_t interval;
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uint8_t error_any:1;
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uint8_t error_stall:1;
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uint8_t alt_next:1;
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uint8_t short_pkt:1;
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uint8_t did_stall:1;
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uint8_t toggle:1;
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uint8_t set_toggle:1;
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};
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struct saf1761_otg_std_temp {
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saf1761_otg_cmd_t *func;
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struct usb_page_cache *pc;
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struct saf1761_otg_td *td;
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struct saf1761_otg_td *td_next;
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uint32_t len;
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uint32_t offset;
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uint16_t max_frame_size;
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uint8_t short_pkt;
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/*
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* short_pkt = 0: transfer should be short terminated
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* short_pkt = 1: transfer should not be short terminated
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*/
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uint8_t setup_alt_next;
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uint8_t did_stall;
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};
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struct saf1761_otg_config_desc {
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struct usb_config_descriptor confd;
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struct usb_interface_descriptor ifcd;
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struct usb_endpoint_descriptor endpd;
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} __packed;
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union saf1761_otg_hub_temp {
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uWord wValue;
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struct usb_port_status ps;
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};
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struct saf1761_otg_flags {
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uint8_t change_connect:1;
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uint8_t change_suspend:1;
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uint8_t status_suspend:1; /* set if suspended */
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uint8_t status_vbus:1; /* set if present */
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uint8_t status_bus_reset:1; /* set if reset complete */
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uint8_t clocks_off:1;
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t d_pulled_up:1;
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};
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struct saf1761_otg_softc {
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struct usb_bus sc_bus;
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union saf1761_otg_hub_temp sc_hub_temp;
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struct usb_device *sc_devices[SOTG_MAX_DEVICES];
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struct resource *sc_io_res;
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struct resource *sc_irq_res;
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void *sc_intr_hdl;
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bus_size_t sc_io_size;
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bus_space_tag_t sc_io_tag;
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bus_space_handle_t sc_io_hdl;
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uint32_t sc_host_async_map;
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uint32_t sc_host_intr_map;
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uint32_t sc_host_isoc_map;
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uint32_t sc_intr_enable; /* enabled interrupts */
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uint32_t sc_hw_mode; /* hardware mode */
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uint32_t sc_interrupt_cfg; /* interrupt configuration */
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uint32_t sc_bounce_buffer[1024 / 4];
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uint8_t sc_rt_addr; /* root HUB address */
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uint8_t sc_dv_addr; /* device address */
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uint8_t sc_conf; /* root HUB config */
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uint8_t sc_isreset; /* host mode */
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uint8_t sc_hub_idata[1];
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struct saf1761_otg_flags sc_flags;
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};
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/* prototypes */
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usb_error_t saf1761_otg_init(struct saf1761_otg_softc *sc);
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void saf1761_otg_uninit(struct saf1761_otg_softc *sc);
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void saf1761_otg_interrupt(struct saf1761_otg_softc *sc);
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#endif /* _SAF1761_OTG_H_ */
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