0070160cea
This is a bit hackish and should be made more generic (ie, support more than two hard-coded performance counter+config register pairs) so it can be used for mips74k and other chips. All this does is process the initial interrupt event. It doesn't (yet) handle callgraph events, so even if you route the exception/interrupt to this routine and flip the bit on, it will hang and crash pmc unless you disable callgraph support when you enable a sample based PMC. |
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.. | ||
hwpmc_amd.c | ||
hwpmc_amd.h | ||
hwpmc_arm.c | ||
hwpmc_core.c | ||
hwpmc_core.h | ||
hwpmc_ia64.c | ||
hwpmc_intel.c | ||
hwpmc_logging.c | ||
hwpmc_mips24k.c | ||
hwpmc_mips24k.h | ||
hwpmc_mips.c | ||
hwpmc_mod.c | ||
hwpmc_pentium.c | ||
hwpmc_pentium.h | ||
hwpmc_piv.c | ||
hwpmc_piv.h | ||
hwpmc_powerpc.c | ||
hwpmc_ppro.c | ||
hwpmc_ppro.h | ||
hwpmc_sparc64.c | ||
hwpmc_tsc.c | ||
hwpmc_tsc.h | ||
hwpmc_uncore.c | ||
hwpmc_uncore.h | ||
hwpmc_x86.c | ||
hwpmc_xscale.c | ||
hwpmc_xscale.h | ||
pmc_events.h |